forked from OSchip/llvm-project
1281 lines
48 KiB
C++
1281 lines
48 KiB
C++
//===- TargetPassConfig.cpp - Target independent code generation passes ---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines interfaces to access the target independent code
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// generation passes provided by the LLVM backend.
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//
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//===---------------------------------------------------------------------===//
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Analysis/BasicAliasAnalysis.h"
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#include "llvm/Analysis/CFLAndersAliasAnalysis.h"
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#include "llvm/Analysis/CFLSteensAliasAnalysis.h"
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#include "llvm/Analysis/CallGraphSCCPass.h"
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#include "llvm/Analysis/ScopedNoAliasAA.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
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#include "llvm/CodeGen/CSEConfigBase.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachinePassRegistry.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/IR/IRPrintingPasses.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/IR/Verifier.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/SaveAndRestore.h"
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#include "llvm/Support/Threading.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Transforms/Utils.h"
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#include "llvm/Transforms/Utils/SymbolRewriter.h"
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#include <cassert>
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#include <string>
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using namespace llvm;
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static cl::opt<bool>
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EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
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cl::desc("Enable interprocedural register allocation "
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"to reduce load/store at procedure calls."));
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static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
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cl::desc("Disable Post Regalloc Scheduler"));
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static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
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cl::desc("Disable branch folding"));
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static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
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cl::desc("Disable tail duplication"));
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static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
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cl::desc("Disable pre-register allocation tail duplication"));
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static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
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cl::Hidden, cl::desc("Disable probability-driven block placement"));
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static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
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cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
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static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
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cl::desc("Disable Stack Slot Coloring"));
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static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
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cl::desc("Disable Machine Dead Code Elimination"));
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static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
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cl::desc("Disable Early If-conversion"));
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static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
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cl::desc("Disable Machine LICM"));
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static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
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cl::desc("Disable Machine Common Subexpression Elimination"));
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static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
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"optimize-regalloc", cl::Hidden,
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cl::desc("Enable optimized register allocation compilation path."));
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static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
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cl::Hidden,
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cl::desc("Disable Machine LICM"));
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static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
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cl::desc("Disable Machine Sinking"));
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static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
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cl::Hidden,
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cl::desc("Disable PostRA Machine Sinking"));
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static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
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cl::desc("Disable Loop Strength Reduction Pass"));
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static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
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cl::Hidden, cl::desc("Disable ConstantHoisting"));
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static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
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cl::desc("Disable Codegen Prepare"));
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static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
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cl::desc("Disable Copy Propagation pass"));
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static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
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cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
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static cl::opt<bool> EnableImplicitNullChecks(
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"enable-implicit-null-checks",
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cl::desc("Fold null checks into faulting memory operations"),
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cl::init(false), cl::Hidden);
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static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
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cl::desc("Disable MergeICmps Pass"),
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cl::init(false), cl::Hidden);
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static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
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cl::desc("Print LLVM IR produced by the loop-reduce pass"));
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static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
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cl::desc("Print LLVM IR input to isel pass"));
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static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
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cl::desc("Dump garbage collector data"));
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static cl::opt<cl::boolOrDefault>
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VerifyMachineCode("verify-machineinstrs", cl::Hidden,
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cl::desc("Verify generated machine code"),
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cl::ZeroOrMore);
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static cl::opt<cl::boolOrDefault> DebugifyAndStripAll(
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"debugify-and-strip-all-safe", cl::Hidden,
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cl::desc(
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"Debugify MIR before and Strip debug after "
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"each pass except those known to be unsafe when debug info is present"),
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cl::ZeroOrMore);
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enum RunOutliner { AlwaysOutline, NeverOutline, TargetDefault };
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// Enable or disable the MachineOutliner.
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static cl::opt<RunOutliner> EnableMachineOutliner(
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"enable-machine-outliner", cl::desc("Enable the machine outliner"),
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cl::Hidden, cl::ValueOptional, cl::init(TargetDefault),
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cl::values(clEnumValN(AlwaysOutline, "always",
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"Run on all functions guaranteed to be beneficial"),
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clEnumValN(NeverOutline, "never", "Disable all outlining"),
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// Sentinel value for unspecified option.
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clEnumValN(AlwaysOutline, "", "")));
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// Enable or disable FastISel. Both options are needed, because
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// FastISel is enabled by default with -fast, and we wish to be
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// able to enable or disable fast-isel independently from -O0.
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static cl::opt<cl::boolOrDefault>
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EnableFastISelOption("fast-isel", cl::Hidden,
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cl::desc("Enable the \"fast\" instruction selector"));
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static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
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"global-isel", cl::Hidden,
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cl::desc("Enable the \"global\" instruction selector"));
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// FIXME: remove this after switching to NPM or GlobalISel, whichever gets there
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// first...
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static cl::opt<bool>
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PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden,
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cl::desc("Print machine instrs after ISel"));
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static cl::opt<GlobalISelAbortMode> EnableGlobalISelAbort(
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"global-isel-abort", cl::Hidden,
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cl::desc("Enable abort calls when \"global\" instruction selection "
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"fails to lower/select an instruction"),
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cl::values(
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clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
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clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
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clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2",
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"Disable the abort but emit a diagnostic on failure")));
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// Temporary option to allow experimenting with MachineScheduler as a post-RA
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// scheduler. Targets can "properly" enable this with
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// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
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// Targets can return true in targetSchedulesPostRAScheduling() and
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// insert a PostRA scheduling pass wherever it wants.
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static cl::opt<bool> MISchedPostRA(
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"misched-postra", cl::Hidden,
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cl::desc(
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"Run MachineScheduler post regalloc (independent of preRA sched)"));
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// Experimental option to run live interval analysis early.
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static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
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cl::desc("Run live interval analysis earlier in the pipeline"));
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// Experimental option to use CFL-AA in codegen
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enum class CFLAAType { None, Steensgaard, Andersen, Both };
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static cl::opt<CFLAAType> UseCFLAA(
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"use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
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cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
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cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
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clEnumValN(CFLAAType::Steensgaard, "steens",
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"Enable unification-based CFL-AA"),
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clEnumValN(CFLAAType::Andersen, "anders",
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"Enable inclusion-based CFL-AA"),
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clEnumValN(CFLAAType::Both, "both",
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"Enable both variants of CFL-AA")));
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/// Option names for limiting the codegen pipeline.
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/// Those are used in error reporting and we didn't want
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/// to duplicate their names all over the place.
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static const char StartAfterOptName[] = "start-after";
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static const char StartBeforeOptName[] = "start-before";
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static const char StopAfterOptName[] = "stop-after";
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static const char StopBeforeOptName[] = "stop-before";
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static cl::opt<std::string>
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StartAfterOpt(StringRef(StartAfterOptName),
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cl::desc("Resume compilation after a specific pass"),
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cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
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static cl::opt<std::string>
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StartBeforeOpt(StringRef(StartBeforeOptName),
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cl::desc("Resume compilation before a specific pass"),
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cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
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static cl::opt<std::string>
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StopAfterOpt(StringRef(StopAfterOptName),
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cl::desc("Stop compilation after a specific pass"),
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cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
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static cl::opt<std::string>
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StopBeforeOpt(StringRef(StopBeforeOptName),
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cl::desc("Stop compilation before a specific pass"),
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cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
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/// Allow standard passes to be disabled by command line options. This supports
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/// simple binary flags that either suppress the pass or do nothing.
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/// i.e. -disable-mypass=false has no effect.
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/// These should be converted to boolOrDefault in order to use applyOverride.
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static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
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bool Override) {
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if (Override)
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return IdentifyingPassPtr();
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return PassID;
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}
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/// Allow standard passes to be disabled by the command line, regardless of who
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/// is adding the pass.
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///
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/// StandardID is the pass identified in the standard pass pipeline and provided
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/// to addPass(). It may be a target-specific ID in the case that the target
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/// directly adds its own pass, but in that case we harmlessly fall through.
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///
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/// TargetID is the pass that the target has configured to override StandardID.
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///
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/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
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/// pass to run. This allows multiple options to control a single pass depending
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/// on where in the pipeline that pass is added.
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static IdentifyingPassPtr overridePass(AnalysisID StandardID,
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IdentifyingPassPtr TargetID) {
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if (StandardID == &PostRASchedulerID)
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return applyDisable(TargetID, DisablePostRASched);
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if (StandardID == &BranchFolderPassID)
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return applyDisable(TargetID, DisableBranchFold);
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if (StandardID == &TailDuplicateID)
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return applyDisable(TargetID, DisableTailDuplicate);
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if (StandardID == &EarlyTailDuplicateID)
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return applyDisable(TargetID, DisableEarlyTailDup);
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if (StandardID == &MachineBlockPlacementID)
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return applyDisable(TargetID, DisableBlockPlacement);
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if (StandardID == &StackSlotColoringID)
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return applyDisable(TargetID, DisableSSC);
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if (StandardID == &DeadMachineInstructionElimID)
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return applyDisable(TargetID, DisableMachineDCE);
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if (StandardID == &EarlyIfConverterID)
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return applyDisable(TargetID, DisableEarlyIfConversion);
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if (StandardID == &EarlyMachineLICMID)
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return applyDisable(TargetID, DisableMachineLICM);
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if (StandardID == &MachineCSEID)
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return applyDisable(TargetID, DisableMachineCSE);
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if (StandardID == &MachineLICMID)
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return applyDisable(TargetID, DisablePostRAMachineLICM);
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if (StandardID == &MachineSinkingID)
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return applyDisable(TargetID, DisableMachineSink);
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if (StandardID == &PostRAMachineSinkingID)
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return applyDisable(TargetID, DisablePostRAMachineSink);
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if (StandardID == &MachineCopyPropagationID)
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return applyDisable(TargetID, DisableCopyProp);
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return TargetID;
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}
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//===---------------------------------------------------------------------===//
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/// TargetPassConfig
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//===---------------------------------------------------------------------===//
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INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
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"Target Pass Configuration", false, false)
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char TargetPassConfig::ID = 0;
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namespace {
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struct InsertedPass {
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AnalysisID TargetPassID;
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IdentifyingPassPtr InsertedPassID;
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bool VerifyAfter;
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InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
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bool VerifyAfter)
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: TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
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VerifyAfter(VerifyAfter) {}
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Pass *getInsertedPass() const {
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assert(InsertedPassID.isValid() && "Illegal Pass ID!");
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if (InsertedPassID.isInstance())
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return InsertedPassID.getInstance();
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Pass *NP = Pass::createPass(InsertedPassID.getID());
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assert(NP && "Pass ID not registered");
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return NP;
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}
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};
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} // end anonymous namespace
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namespace llvm {
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class PassConfigImpl {
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public:
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// List of passes explicitly substituted by this target. Normally this is
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// empty, but it is a convenient way to suppress or replace specific passes
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// that are part of a standard pass pipeline without overridding the entire
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// pipeline. This mechanism allows target options to inherit a standard pass's
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// user interface. For example, a target may disable a standard pass by
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// default by substituting a pass ID of zero, and the user may still enable
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// that standard pass with an explicit command line option.
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DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
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/// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
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/// is inserted after each instance of the first one.
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SmallVector<InsertedPass, 4> InsertedPasses;
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};
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} // end namespace llvm
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// Out of line virtual method.
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TargetPassConfig::~TargetPassConfig() {
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delete Impl;
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}
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static const PassInfo *getPassInfo(StringRef PassName) {
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if (PassName.empty())
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return nullptr;
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const PassRegistry &PR = *PassRegistry::getPassRegistry();
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const PassInfo *PI = PR.getPassInfo(PassName);
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if (!PI)
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report_fatal_error(Twine('\"') + Twine(PassName) +
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Twine("\" pass is not registered."));
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return PI;
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}
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static AnalysisID getPassIDFromName(StringRef PassName) {
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const PassInfo *PI = getPassInfo(PassName);
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return PI ? PI->getTypeInfo() : nullptr;
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}
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static std::pair<StringRef, unsigned>
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getPassNameAndInstanceNum(StringRef PassName) {
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StringRef Name, InstanceNumStr;
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std::tie(Name, InstanceNumStr) = PassName.split(',');
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unsigned InstanceNum = 0;
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if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
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report_fatal_error("invalid pass instance specifier " + PassName);
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return std::make_pair(Name, InstanceNum);
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}
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void TargetPassConfig::setStartStopPasses() {
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StringRef StartBeforeName;
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std::tie(StartBeforeName, StartBeforeInstanceNum) =
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getPassNameAndInstanceNum(StartBeforeOpt);
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StringRef StartAfterName;
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std::tie(StartAfterName, StartAfterInstanceNum) =
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getPassNameAndInstanceNum(StartAfterOpt);
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StringRef StopBeforeName;
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std::tie(StopBeforeName, StopBeforeInstanceNum)
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= getPassNameAndInstanceNum(StopBeforeOpt);
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StringRef StopAfterName;
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std::tie(StopAfterName, StopAfterInstanceNum)
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= getPassNameAndInstanceNum(StopAfterOpt);
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StartBefore = getPassIDFromName(StartBeforeName);
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StartAfter = getPassIDFromName(StartAfterName);
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StopBefore = getPassIDFromName(StopBeforeName);
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StopAfter = getPassIDFromName(StopAfterName);
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if (StartBefore && StartAfter)
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report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
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Twine(StartAfterOptName) + Twine(" specified!"));
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if (StopBefore && StopAfter)
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report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
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Twine(StopAfterOptName) + Twine(" specified!"));
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Started = (StartAfter == nullptr) && (StartBefore == nullptr);
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}
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// Out of line constructor provides default values for pass options and
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// registers all common codegen passes.
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TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
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: ImmutablePass(ID), PM(&pm), TM(&TM) {
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Impl = new PassConfigImpl();
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// Register all target independent codegen passes to activate their PassIDs,
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// including this pass itself.
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initializeCodeGen(*PassRegistry::getPassRegistry());
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// Also register alias analysis passes required by codegen passes.
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initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
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initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
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if (EnableIPRA.getNumOccurrences())
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TM.Options.EnableIPRA = EnableIPRA;
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else {
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// If not explicitly specified, use target default.
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TM.Options.EnableIPRA |= TM.useIPRA();
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}
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if (TM.Options.EnableIPRA)
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setRequiresCodeGenSCCOrder();
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if (EnableGlobalISelAbort.getNumOccurrences())
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TM.Options.GlobalISelAbort = EnableGlobalISelAbort;
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setStartStopPasses();
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}
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CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
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return TM->getOptLevel();
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}
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/// Insert InsertedPassID pass after TargetPassID.
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void TargetPassConfig::insertPass(AnalysisID TargetPassID,
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IdentifyingPassPtr InsertedPassID,
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bool VerifyAfter) {
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assert(((!InsertedPassID.isInstance() &&
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TargetPassID != InsertedPassID.getID()) ||
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(InsertedPassID.isInstance() &&
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TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
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"Insert a pass after itself!");
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Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter);
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}
|
|
|
|
/// createPassConfig - Create a pass configuration object to be used by
|
|
/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
|
|
///
|
|
/// Targets may override this to extend TargetPassConfig.
|
|
TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
|
|
return new TargetPassConfig(*this, PM);
|
|
}
|
|
|
|
TargetPassConfig::TargetPassConfig()
|
|
: ImmutablePass(ID) {
|
|
report_fatal_error("Trying to construct TargetPassConfig without a target "
|
|
"machine. Scheduling a CodeGen pass without a target "
|
|
"triple set?");
|
|
}
|
|
|
|
bool TargetPassConfig::willCompleteCodeGenPipeline() {
|
|
return StopBeforeOpt.empty() && StopAfterOpt.empty();
|
|
}
|
|
|
|
bool TargetPassConfig::hasLimitedCodeGenPipeline() {
|
|
return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
|
|
!willCompleteCodeGenPipeline();
|
|
}
|
|
|
|
std::string
|
|
TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) {
|
|
if (!hasLimitedCodeGenPipeline())
|
|
return std::string();
|
|
std::string Res;
|
|
static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
|
|
&StopAfterOpt, &StopBeforeOpt};
|
|
static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
|
|
StopAfterOptName, StopBeforeOptName};
|
|
bool IsFirst = true;
|
|
for (int Idx = 0; Idx < 4; ++Idx)
|
|
if (!PassNames[Idx]->empty()) {
|
|
if (!IsFirst)
|
|
Res += Separator;
|
|
IsFirst = false;
|
|
Res += OptNames[Idx];
|
|
}
|
|
return Res;
|
|
}
|
|
|
|
// Helper to verify the analysis is really immutable.
|
|
void TargetPassConfig::setOpt(bool &Opt, bool Val) {
|
|
assert(!Initialized && "PassConfig is immutable");
|
|
Opt = Val;
|
|
}
|
|
|
|
void TargetPassConfig::substitutePass(AnalysisID StandardID,
|
|
IdentifyingPassPtr TargetID) {
|
|
Impl->TargetPasses[StandardID] = TargetID;
|
|
}
|
|
|
|
IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
|
|
DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
|
|
I = Impl->TargetPasses.find(ID);
|
|
if (I == Impl->TargetPasses.end())
|
|
return ID;
|
|
return I->second;
|
|
}
|
|
|
|
bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
|
|
IdentifyingPassPtr TargetID = getPassSubstitution(ID);
|
|
IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
|
|
return !FinalPtr.isValid() || FinalPtr.isInstance() ||
|
|
FinalPtr.getID() != ID;
|
|
}
|
|
|
|
/// Add a pass to the PassManager if that pass is supposed to be run. If the
|
|
/// Started/Stopped flags indicate either that the compilation should start at
|
|
/// a later pass or that it should stop after an earlier pass, then do not add
|
|
/// the pass. Finally, compare the current pass against the StartAfter
|
|
/// and StopAfter options and change the Started/Stopped flags accordingly.
|
|
void TargetPassConfig::addPass(Pass *P, bool verifyAfter) {
|
|
assert(!Initialized && "PassConfig is immutable");
|
|
|
|
// Cache the Pass ID here in case the pass manager finds this pass is
|
|
// redundant with ones already scheduled / available, and deletes it.
|
|
// Fundamentally, once we add the pass to the manager, we no longer own it
|
|
// and shouldn't reference it.
|
|
AnalysisID PassID = P->getPassID();
|
|
|
|
if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
|
|
Started = true;
|
|
if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
|
|
Stopped = true;
|
|
if (Started && !Stopped) {
|
|
if (AddingMachinePasses)
|
|
addMachinePrePasses();
|
|
std::string Banner;
|
|
// Construct banner message before PM->add() as that may delete the pass.
|
|
if (AddingMachinePasses && verifyAfter)
|
|
Banner = std::string("After ") + std::string(P->getPassName());
|
|
PM->add(P);
|
|
if (AddingMachinePasses)
|
|
addMachinePostPasses(Banner, /*AllowVerify*/ verifyAfter);
|
|
|
|
// Add the passes after the pass P if there is any.
|
|
for (auto IP : Impl->InsertedPasses) {
|
|
if (IP.TargetPassID == PassID)
|
|
addPass(IP.getInsertedPass(), IP.VerifyAfter);
|
|
}
|
|
} else {
|
|
delete P;
|
|
}
|
|
|
|
if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
|
|
Stopped = true;
|
|
|
|
if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
|
|
Started = true;
|
|
if (Stopped && !Started)
|
|
report_fatal_error("Cannot stop compilation after pass that is not run");
|
|
}
|
|
|
|
/// Add a CodeGen pass at this point in the pipeline after checking for target
|
|
/// and command line overrides.
|
|
///
|
|
/// addPass cannot return a pointer to the pass instance because is internal the
|
|
/// PassManager and the instance we create here may already be freed.
|
|
AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter) {
|
|
IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
|
|
IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
|
|
if (!FinalPtr.isValid())
|
|
return nullptr;
|
|
|
|
Pass *P;
|
|
if (FinalPtr.isInstance())
|
|
P = FinalPtr.getInstance();
|
|
else {
|
|
P = Pass::createPass(FinalPtr.getID());
|
|
if (!P)
|
|
llvm_unreachable("Pass ID not registered");
|
|
}
|
|
AnalysisID FinalID = P->getPassID();
|
|
addPass(P, verifyAfter); // Ends the lifetime of P.
|
|
|
|
return FinalID;
|
|
}
|
|
|
|
void TargetPassConfig::printAndVerify(const std::string &Banner) {
|
|
addPrintPass(Banner);
|
|
addVerifyPass(Banner);
|
|
}
|
|
|
|
void TargetPassConfig::addPrintPass(const std::string &Banner) {
|
|
if (PrintAfterISel)
|
|
PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
|
|
}
|
|
|
|
void TargetPassConfig::addVerifyPass(const std::string &Banner) {
|
|
bool Verify = VerifyMachineCode == cl::BOU_TRUE;
|
|
#ifdef EXPENSIVE_CHECKS
|
|
if (VerifyMachineCode == cl::BOU_UNSET)
|
|
Verify = TM->isMachineVerifierClean();
|
|
#endif
|
|
if (Verify)
|
|
PM->add(createMachineVerifierPass(Banner));
|
|
}
|
|
|
|
void TargetPassConfig::addDebugifyPass() {
|
|
PM->add(createDebugifyMachineModulePass());
|
|
}
|
|
|
|
void TargetPassConfig::addStripDebugPass() {
|
|
PM->add(createStripDebugMachineModulePass(/*OnlyDebugified=*/true));
|
|
}
|
|
|
|
void TargetPassConfig::addMachinePrePasses(bool AllowDebugify) {
|
|
if (AllowDebugify && DebugifyAndStripAll == cl::BOU_TRUE && DebugifyIsSafe)
|
|
addDebugifyPass();
|
|
}
|
|
|
|
void TargetPassConfig::addMachinePostPasses(const std::string &Banner,
|
|
bool AllowVerify, bool AllowStrip) {
|
|
if (DebugifyAndStripAll == cl::BOU_TRUE && DebugifyIsSafe)
|
|
addStripDebugPass();
|
|
if (AllowVerify)
|
|
addVerifyPass(Banner);
|
|
}
|
|
|
|
/// Add common target configurable passes that perform LLVM IR to IR transforms
|
|
/// following machine independent optimization.
|
|
void TargetPassConfig::addIRPasses() {
|
|
// Before running any passes, run the verifier to determine if the input
|
|
// coming from the front-end and/or optimizer is valid.
|
|
if (!DisableVerify)
|
|
addPass(createVerifierPass());
|
|
|
|
if (getOptLevel() != CodeGenOpt::None) {
|
|
switch (UseCFLAA) {
|
|
case CFLAAType::Steensgaard:
|
|
addPass(createCFLSteensAAWrapperPass());
|
|
break;
|
|
case CFLAAType::Andersen:
|
|
addPass(createCFLAndersAAWrapperPass());
|
|
break;
|
|
case CFLAAType::Both:
|
|
addPass(createCFLAndersAAWrapperPass());
|
|
addPass(createCFLSteensAAWrapperPass());
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
// Basic AliasAnalysis support.
|
|
// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
|
|
// BasicAliasAnalysis wins if they disagree. This is intended to help
|
|
// support "obvious" type-punning idioms.
|
|
addPass(createTypeBasedAAWrapperPass());
|
|
addPass(createScopedNoAliasAAWrapperPass());
|
|
addPass(createBasicAAWrapperPass());
|
|
|
|
// Run loop strength reduction before anything else.
|
|
if (!DisableLSR) {
|
|
addPass(createCanonicalizeFreezeInLoopsPass());
|
|
addPass(createLoopStrengthReducePass());
|
|
if (PrintLSR)
|
|
addPass(createPrintFunctionPass(dbgs(),
|
|
"\n\n*** Code after LSR ***\n"));
|
|
}
|
|
|
|
// The MergeICmpsPass tries to create memcmp calls by grouping sequences of
|
|
// loads and compares. ExpandMemCmpPass then tries to expand those calls
|
|
// into optimally-sized loads and compares. The transforms are enabled by a
|
|
// target lowering hook.
|
|
if (!DisableMergeICmps)
|
|
addPass(createMergeICmpsLegacyPass());
|
|
addPass(createExpandMemCmpPass());
|
|
}
|
|
|
|
// Run GC lowering passes for builtin collectors
|
|
// TODO: add a pass insertion point here
|
|
addPass(createGCLoweringPass());
|
|
addPass(createShadowStackGCLoweringPass());
|
|
addPass(createLowerConstantIntrinsicsPass());
|
|
|
|
// Make sure that no unreachable blocks are instruction selected.
|
|
addPass(createUnreachableBlockEliminationPass());
|
|
|
|
// Prepare expensive constants for SelectionDAG.
|
|
if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
|
|
addPass(createConstantHoistingPass());
|
|
|
|
if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
|
|
addPass(createPartiallyInlineLibCallsPass());
|
|
|
|
// Instrument function entry and exit, e.g. with calls to mcount().
|
|
addPass(createPostInlineEntryExitInstrumenterPass());
|
|
|
|
// Add scalarization of target's unsupported masked memory intrinsics pass.
|
|
// the unsupported intrinsic will be replaced with a chain of basic blocks,
|
|
// that stores/loads element one-by-one if the appropriate mask bit is set.
|
|
addPass(createScalarizeMaskedMemIntrinPass());
|
|
|
|
// Expand reduction intrinsics into shuffle sequences if the target wants to.
|
|
addPass(createExpandReductionsPass());
|
|
}
|
|
|
|
/// Turn exception handling constructs into something the code generators can
|
|
/// handle.
|
|
void TargetPassConfig::addPassesToHandleExceptions() {
|
|
const MCAsmInfo *MCAI = TM->getMCAsmInfo();
|
|
assert(MCAI && "No MCAsmInfo");
|
|
switch (MCAI->getExceptionHandlingType()) {
|
|
case ExceptionHandling::SjLj:
|
|
// SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
|
|
// Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
|
|
// catch info can get misplaced when a selector ends up more than one block
|
|
// removed from the parent invoke(s). This could happen when a landing
|
|
// pad is shared by multiple invokes and is also a target of a normal
|
|
// edge from elsewhere.
|
|
addPass(createSjLjEHPreparePass(TM));
|
|
LLVM_FALLTHROUGH;
|
|
case ExceptionHandling::DwarfCFI:
|
|
case ExceptionHandling::ARM:
|
|
addPass(createDwarfEHPass(getOptLevel()));
|
|
break;
|
|
case ExceptionHandling::WinEH:
|
|
// We support using both GCC-style and MSVC-style exceptions on Windows, so
|
|
// add both preparation passes. Each pass will only actually run if it
|
|
// recognizes the personality function.
|
|
addPass(createWinEHPass());
|
|
addPass(createDwarfEHPass(getOptLevel()));
|
|
break;
|
|
case ExceptionHandling::Wasm:
|
|
// Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
|
|
// on catchpads and cleanuppads because it does not outline them into
|
|
// funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
|
|
// should remove PHIs there.
|
|
addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
|
|
addPass(createWasmEHPass());
|
|
break;
|
|
case ExceptionHandling::None:
|
|
addPass(createLowerInvokePass());
|
|
|
|
// The lower invoke pass may create unreachable code. Remove it.
|
|
addPass(createUnreachableBlockEliminationPass());
|
|
break;
|
|
}
|
|
}
|
|
|
|
/// Add pass to prepare the LLVM IR for code generation. This should be done
|
|
/// before exception handling preparation passes.
|
|
void TargetPassConfig::addCodeGenPrepare() {
|
|
if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
|
|
addPass(createCodeGenPreparePass());
|
|
addPass(createRewriteSymbolsPass());
|
|
}
|
|
|
|
/// Add common passes that perform LLVM IR to IR transforms in preparation for
|
|
/// instruction selection.
|
|
void TargetPassConfig::addISelPrepare() {
|
|
addPreISel();
|
|
|
|
// Force codegen to run according to the callgraph.
|
|
if (requiresCodeGenSCCOrder())
|
|
addPass(new DummyCGSCCPass);
|
|
|
|
// Add both the safe stack and the stack protection passes: each of them will
|
|
// only protect functions that have corresponding attributes.
|
|
addPass(createSafeStackPass());
|
|
addPass(createStackProtectorPass());
|
|
|
|
if (PrintISelInput)
|
|
addPass(createPrintFunctionPass(
|
|
dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
|
|
|
|
// All passes which modify the LLVM IR are now complete; run the verifier
|
|
// to ensure that the IR is valid.
|
|
if (!DisableVerify)
|
|
addPass(createVerifierPass());
|
|
}
|
|
|
|
bool TargetPassConfig::addCoreISelPasses() {
|
|
// Enable FastISel with -fast-isel, but allow that to be overridden.
|
|
TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
|
|
|
|
// Determine an instruction selector.
|
|
enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
|
|
SelectorType Selector;
|
|
|
|
if (EnableFastISelOption == cl::BOU_TRUE)
|
|
Selector = SelectorType::FastISel;
|
|
else if (EnableGlobalISelOption == cl::BOU_TRUE ||
|
|
(TM->Options.EnableGlobalISel &&
|
|
EnableGlobalISelOption != cl::BOU_FALSE))
|
|
Selector = SelectorType::GlobalISel;
|
|
else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel())
|
|
Selector = SelectorType::FastISel;
|
|
else
|
|
Selector = SelectorType::SelectionDAG;
|
|
|
|
// Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
|
|
if (Selector == SelectorType::FastISel) {
|
|
TM->setFastISel(true);
|
|
TM->setGlobalISel(false);
|
|
} else if (Selector == SelectorType::GlobalISel) {
|
|
TM->setFastISel(false);
|
|
TM->setGlobalISel(true);
|
|
}
|
|
|
|
// FIXME: Injecting into the DAGISel pipeline seems to cause issues with
|
|
// analyses needing to be re-run. This can result in being unable to
|
|
// schedule passes (particularly with 'Function Alias Analysis
|
|
// Results'). It's not entirely clear why but AFAICT this seems to be
|
|
// due to one FunctionPassManager not being able to use analyses from a
|
|
// previous one. As we're injecting a ModulePass we break the usual
|
|
// pass manager into two. GlobalISel with the fallback path disabled
|
|
// and -run-pass seem to be unaffected. The majority of GlobalISel
|
|
// testing uses -run-pass so this probably isn't too bad.
|
|
SaveAndRestore<bool> SavedDebugifyIsSafe(DebugifyIsSafe);
|
|
if (Selector != SelectorType::GlobalISel || !isGlobalISelAbortEnabled())
|
|
DebugifyIsSafe = false;
|
|
|
|
// Add instruction selector passes.
|
|
if (Selector == SelectorType::GlobalISel) {
|
|
SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
|
|
if (addIRTranslator())
|
|
return true;
|
|
|
|
addPreLegalizeMachineIR();
|
|
|
|
if (addLegalizeMachineIR())
|
|
return true;
|
|
|
|
// Before running the register bank selector, ask the target if it
|
|
// wants to run some passes.
|
|
addPreRegBankSelect();
|
|
|
|
if (addRegBankSelect())
|
|
return true;
|
|
|
|
addPreGlobalInstructionSelect();
|
|
|
|
if (addGlobalInstructionSelect())
|
|
return true;
|
|
|
|
// Pass to reset the MachineFunction if the ISel failed.
|
|
addPass(createResetMachineFunctionPass(
|
|
reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled()));
|
|
|
|
// Provide a fallback path when we do not want to abort on
|
|
// not-yet-supported input.
|
|
if (!isGlobalISelAbortEnabled() && addInstSelector())
|
|
return true;
|
|
|
|
} else if (addInstSelector())
|
|
return true;
|
|
|
|
// Expand pseudo-instructions emitted by ISel. Don't run the verifier before
|
|
// FinalizeISel.
|
|
addPass(&FinalizeISelID);
|
|
|
|
// Print the instruction selected machine code...
|
|
printAndVerify("After Instruction Selection");
|
|
|
|
return false;
|
|
}
|
|
|
|
bool TargetPassConfig::addISelPasses() {
|
|
if (TM->useEmulatedTLS())
|
|
addPass(createLowerEmuTLSPass());
|
|
|
|
addPass(createPreISelIntrinsicLoweringPass());
|
|
PM->add(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
|
|
addIRPasses();
|
|
addCodeGenPrepare();
|
|
addPassesToHandleExceptions();
|
|
addISelPrepare();
|
|
|
|
return addCoreISelPasses();
|
|
}
|
|
|
|
/// -regalloc=... command line option.
|
|
static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
|
|
static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
|
|
RegisterPassParser<RegisterRegAlloc>>
|
|
RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
|
|
cl::desc("Register allocator to use"));
|
|
|
|
/// Add the complete set of target-independent postISel code generator passes.
|
|
///
|
|
/// This can be read as the standard order of major LLVM CodeGen stages. Stages
|
|
/// with nontrivial configuration or multiple passes are broken out below in
|
|
/// add%Stage routines.
|
|
///
|
|
/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
|
|
/// addPre/Post methods with empty header implementations allow injecting
|
|
/// target-specific fixups just before or after major stages. Additionally,
|
|
/// targets have the flexibility to change pass order within a stage by
|
|
/// overriding default implementation of add%Stage routines below. Each
|
|
/// technique has maintainability tradeoffs because alternate pass orders are
|
|
/// not well supported. addPre/Post works better if the target pass is easily
|
|
/// tied to a common pass. But if it has subtle dependencies on multiple passes,
|
|
/// the target should override the stage instead.
|
|
///
|
|
/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
|
|
/// before/after any target-independent pass. But it's currently overkill.
|
|
void TargetPassConfig::addMachinePasses() {
|
|
AddingMachinePasses = true;
|
|
|
|
// Add passes that optimize machine instructions in SSA form.
|
|
if (getOptLevel() != CodeGenOpt::None) {
|
|
addMachineSSAOptimization();
|
|
} else {
|
|
// If the target requests it, assign local variables to stack slots relative
|
|
// to one another and simplify frame index references where possible.
|
|
addPass(&LocalStackSlotAllocationID);
|
|
}
|
|
|
|
if (TM->Options.EnableIPRA)
|
|
addPass(createRegUsageInfoPropPass());
|
|
|
|
// Run pre-ra passes.
|
|
addPreRegAlloc();
|
|
|
|
// Debugifying the register allocator passes seems to provoke some
|
|
// non-determinism that affects CodeGen and there doesn't seem to be a point
|
|
// where it becomes safe again so stop debugifying here.
|
|
DebugifyIsSafe = false;
|
|
|
|
// Run register allocation and passes that are tightly coupled with it,
|
|
// including phi elimination and scheduling.
|
|
if (getOptimizeRegAlloc())
|
|
addOptimizedRegAlloc();
|
|
else
|
|
addFastRegAlloc();
|
|
|
|
// Run post-ra passes.
|
|
addPostRegAlloc();
|
|
|
|
addPass(&FixupStatepointCallerSavedID);
|
|
|
|
// Insert prolog/epilog code. Eliminate abstract frame index references...
|
|
if (getOptLevel() != CodeGenOpt::None) {
|
|
addPass(&PostRAMachineSinkingID);
|
|
addPass(&ShrinkWrapID);
|
|
}
|
|
|
|
// Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
|
|
// do so if it hasn't been disabled, substituted, or overridden.
|
|
if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
|
|
addPass(createPrologEpilogInserterPass());
|
|
|
|
/// Add passes that optimize machine instructions after register allocation.
|
|
if (getOptLevel() != CodeGenOpt::None)
|
|
addMachineLateOptimization();
|
|
|
|
// Expand pseudo instructions before second scheduling pass.
|
|
addPass(&ExpandPostRAPseudosID);
|
|
|
|
// Run pre-sched2 passes.
|
|
addPreSched2();
|
|
|
|
if (EnableImplicitNullChecks)
|
|
addPass(&ImplicitNullChecksID);
|
|
|
|
// Second pass scheduler.
|
|
// Let Target optionally insert this pass by itself at some other
|
|
// point.
|
|
if (getOptLevel() != CodeGenOpt::None &&
|
|
!TM->targetSchedulesPostRAScheduling()) {
|
|
if (MISchedPostRA)
|
|
addPass(&PostMachineSchedulerID);
|
|
else
|
|
addPass(&PostRASchedulerID);
|
|
}
|
|
|
|
// GC
|
|
if (addGCPasses()) {
|
|
if (PrintGCInfo)
|
|
addPass(createGCInfoPrinter(dbgs()), false);
|
|
}
|
|
|
|
// Basic block placement.
|
|
if (getOptLevel() != CodeGenOpt::None)
|
|
addBlockPlacement();
|
|
|
|
// Insert before XRay Instrumentation.
|
|
addPass(&FEntryInserterID);
|
|
|
|
addPass(&XRayInstrumentationID);
|
|
addPass(&PatchableFunctionID);
|
|
|
|
addPreEmitPass();
|
|
|
|
if (TM->Options.EnableIPRA)
|
|
// Collect register usage information and produce a register mask of
|
|
// clobbered registers, to be used to optimize call sites.
|
|
addPass(createRegUsageInfoCollector());
|
|
|
|
// FIXME: Some backends are incompatible with running the verifier after
|
|
// addPreEmitPass. Maybe only pass "false" here for those targets?
|
|
addPass(&FuncletLayoutID, false);
|
|
|
|
addPass(&StackMapLivenessID, false);
|
|
addPass(&LiveDebugValuesID, false);
|
|
|
|
if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
|
|
EnableMachineOutliner != NeverOutline) {
|
|
bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline);
|
|
bool AddOutliner = RunOnAllFunctions ||
|
|
TM->Options.SupportsDefaultOutlining;
|
|
if (AddOutliner)
|
|
addPass(createMachineOutlinerPass(RunOnAllFunctions));
|
|
}
|
|
|
|
if (TM->getBBSectionsType() != llvm::BasicBlockSection::None)
|
|
addPass(llvm::createBasicBlockSectionsPass(TM->getBBSectionsFuncListBuf()));
|
|
|
|
// Add passes that directly emit MI after all other MI passes.
|
|
addPreEmitPass2();
|
|
|
|
AddingMachinePasses = false;
|
|
}
|
|
|
|
/// Add passes that optimize machine instructions in SSA form.
|
|
void TargetPassConfig::addMachineSSAOptimization() {
|
|
// Pre-ra tail duplication.
|
|
addPass(&EarlyTailDuplicateID);
|
|
|
|
// Optimize PHIs before DCE: removing dead PHI cycles may make more
|
|
// instructions dead.
|
|
addPass(&OptimizePHIsID);
|
|
|
|
// This pass merges large allocas. StackSlotColoring is a different pass
|
|
// which merges spill slots.
|
|
addPass(&StackColoringID);
|
|
|
|
// If the target requests it, assign local variables to stack slots relative
|
|
// to one another and simplify frame index references where possible.
|
|
addPass(&LocalStackSlotAllocationID);
|
|
|
|
// With optimization, dead code should already be eliminated. However
|
|
// there is one known exception: lowered code for arguments that are only
|
|
// used by tail calls, where the tail calls reuse the incoming stack
|
|
// arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
|
|
addPass(&DeadMachineInstructionElimID);
|
|
|
|
// Allow targets to insert passes that improve instruction level parallelism,
|
|
// like if-conversion. Such passes will typically need dominator trees and
|
|
// loop info, just like LICM and CSE below.
|
|
addILPOpts();
|
|
|
|
addPass(&EarlyMachineLICMID);
|
|
addPass(&MachineCSEID);
|
|
|
|
addPass(&MachineSinkingID);
|
|
|
|
addPass(&PeepholeOptimizerID);
|
|
// Clean-up the dead code that may have been generated by peephole
|
|
// rewriting.
|
|
addPass(&DeadMachineInstructionElimID);
|
|
}
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
/// Register Allocation Pass Configuration
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
bool TargetPassConfig::getOptimizeRegAlloc() const {
|
|
switch (OptimizeRegAlloc) {
|
|
case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
|
|
case cl::BOU_TRUE: return true;
|
|
case cl::BOU_FALSE: return false;
|
|
}
|
|
llvm_unreachable("Invalid optimize-regalloc state");
|
|
}
|
|
|
|
/// A dummy default pass factory indicates whether the register allocator is
|
|
/// overridden on the command line.
|
|
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
|
|
|
|
static RegisterRegAlloc
|
|
defaultRegAlloc("default",
|
|
"pick register allocator based on -O option",
|
|
useDefaultRegisterAllocator);
|
|
|
|
static void initializeDefaultRegisterAllocatorOnce() {
|
|
if (!RegisterRegAlloc::getDefault())
|
|
RegisterRegAlloc::setDefault(RegAlloc);
|
|
}
|
|
|
|
/// Instantiate the default register allocator pass for this target for either
|
|
/// the optimized or unoptimized allocation path. This will be added to the pass
|
|
/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
|
|
/// in the optimized case.
|
|
///
|
|
/// A target that uses the standard regalloc pass order for fast or optimized
|
|
/// allocation may still override this for per-target regalloc
|
|
/// selection. But -regalloc=... always takes precedence.
|
|
FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
|
|
if (Optimized)
|
|
return createGreedyRegisterAllocator();
|
|
else
|
|
return createFastRegisterAllocator();
|
|
}
|
|
|
|
/// Find and instantiate the register allocation pass requested by this target
|
|
/// at the current optimization level. Different register allocators are
|
|
/// defined as separate passes because they may require different analysis.
|
|
///
|
|
/// This helper ensures that the regalloc= option is always available,
|
|
/// even for targets that override the default allocator.
|
|
///
|
|
/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
|
|
/// this can be folded into addPass.
|
|
FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
|
|
// Initialize the global default.
|
|
llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
|
|
initializeDefaultRegisterAllocatorOnce);
|
|
|
|
RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
|
|
if (Ctor != useDefaultRegisterAllocator)
|
|
return Ctor();
|
|
|
|
// With no -regalloc= override, ask the target for a regalloc pass.
|
|
return createTargetRegisterAllocator(Optimized);
|
|
}
|
|
|
|
bool TargetPassConfig::addRegAssignmentFast() {
|
|
if (RegAlloc != &useDefaultRegisterAllocator &&
|
|
RegAlloc != &createFastRegisterAllocator)
|
|
report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
|
|
|
|
addPass(createRegAllocPass(false));
|
|
return true;
|
|
}
|
|
|
|
bool TargetPassConfig::addRegAssignmentOptimized() {
|
|
// Add the selected register allocation pass.
|
|
addPass(createRegAllocPass(true));
|
|
|
|
// Allow targets to change the register assignments before rewriting.
|
|
addPreRewrite();
|
|
|
|
// Finally rewrite virtual registers.
|
|
addPass(&VirtRegRewriterID);
|
|
|
|
// Perform stack slot coloring and post-ra machine LICM.
|
|
//
|
|
// FIXME: Re-enable coloring with register when it's capable of adding
|
|
// kill markers.
|
|
addPass(&StackSlotColoringID);
|
|
|
|
return true;
|
|
}
|
|
|
|
/// Return true if the default global register allocator is in use and
|
|
/// has not be overriden on the command line with '-regalloc=...'
|
|
bool TargetPassConfig::usingDefaultRegAlloc() const {
|
|
return RegAlloc.getNumOccurrences() == 0;
|
|
}
|
|
|
|
/// Add the minimum set of target-independent passes that are required for
|
|
/// register allocation. No coalescing or scheduling.
|
|
void TargetPassConfig::addFastRegAlloc() {
|
|
addPass(&PHIEliminationID, false);
|
|
addPass(&TwoAddressInstructionPassID, false);
|
|
|
|
addRegAssignmentFast();
|
|
}
|
|
|
|
/// Add standard target-independent passes that are tightly coupled with
|
|
/// optimized register allocation, including coalescing, machine instruction
|
|
/// scheduling, and register allocation itself.
|
|
void TargetPassConfig::addOptimizedRegAlloc() {
|
|
addPass(&DetectDeadLanesID, false);
|
|
|
|
addPass(&ProcessImplicitDefsID, false);
|
|
|
|
// LiveVariables currently requires pure SSA form.
|
|
//
|
|
// FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
|
|
// LiveVariables can be removed completely, and LiveIntervals can be directly
|
|
// computed. (We still either need to regenerate kill flags after regalloc, or
|
|
// preferably fix the scavenger to not depend on them).
|
|
// FIXME: UnreachableMachineBlockElim is a dependant pass of LiveVariables.
|
|
// When LiveVariables is removed this has to be removed/moved either.
|
|
// Explicit addition of UnreachableMachineBlockElim allows stopping before or
|
|
// after it with -stop-before/-stop-after.
|
|
addPass(&UnreachableMachineBlockElimID, false);
|
|
addPass(&LiveVariablesID, false);
|
|
|
|
// Edge splitting is smarter with machine loop info.
|
|
addPass(&MachineLoopInfoID, false);
|
|
addPass(&PHIEliminationID, false);
|
|
|
|
// Eventually, we want to run LiveIntervals before PHI elimination.
|
|
if (EarlyLiveIntervals)
|
|
addPass(&LiveIntervalsID, false);
|
|
|
|
addPass(&TwoAddressInstructionPassID, false);
|
|
addPass(&RegisterCoalescerID);
|
|
|
|
// The machine scheduler may accidentally create disconnected components
|
|
// when moving subregister definitions around, avoid this by splitting them to
|
|
// separate vregs before. Splitting can also improve reg. allocation quality.
|
|
addPass(&RenameIndependentSubregsID);
|
|
|
|
// PreRA instruction scheduling.
|
|
addPass(&MachineSchedulerID);
|
|
|
|
if (addRegAssignmentOptimized()) {
|
|
// Allow targets to expand pseudo instructions depending on the choice of
|
|
// registers before MachineCopyPropagation.
|
|
addPostRewrite();
|
|
|
|
// Copy propagate to forward register uses and try to eliminate COPYs that
|
|
// were not coalesced.
|
|
addPass(&MachineCopyPropagationID);
|
|
|
|
// Run post-ra machine LICM to hoist reloads / remats.
|
|
//
|
|
// FIXME: can this move into MachineLateOptimization?
|
|
addPass(&MachineLICMID);
|
|
}
|
|
}
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
/// Post RegAlloc Pass Configuration
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
/// Add passes that optimize machine instructions after register allocation.
|
|
void TargetPassConfig::addMachineLateOptimization() {
|
|
// Branch folding must be run after regalloc and prolog/epilog insertion.
|
|
addPass(&BranchFolderPassID);
|
|
|
|
// Tail duplication.
|
|
// Note that duplicating tail just increases code size and degrades
|
|
// performance for targets that require Structured Control Flow.
|
|
// In addition it can also make CFG irreducible. Thus we disable it.
|
|
if (!TM->requiresStructuredCFG())
|
|
addPass(&TailDuplicateID);
|
|
|
|
// Copy propagation.
|
|
addPass(&MachineCopyPropagationID);
|
|
}
|
|
|
|
/// Add standard GC passes.
|
|
bool TargetPassConfig::addGCPasses() {
|
|
addPass(&GCMachineCodeAnalysisID, false);
|
|
return true;
|
|
}
|
|
|
|
/// Add standard basic block placement passes.
|
|
void TargetPassConfig::addBlockPlacement() {
|
|
if (addPass(&MachineBlockPlacementID)) {
|
|
// Run a separate pass to collect block placement statistics.
|
|
if (EnableBlockPlacementStats)
|
|
addPass(&MachineBlockPlacementStatsID);
|
|
}
|
|
}
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
/// GlobalISel Configuration
|
|
//===---------------------------------------------------------------------===//
|
|
bool TargetPassConfig::isGlobalISelAbortEnabled() const {
|
|
return TM->Options.GlobalISelAbort == GlobalISelAbortMode::Enable;
|
|
}
|
|
|
|
bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
|
|
return TM->Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag;
|
|
}
|
|
|
|
bool TargetPassConfig::isGISelCSEEnabled() const {
|
|
return true;
|
|
}
|
|
|
|
std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const {
|
|
return std::make_unique<CSEConfigBase>();
|
|
}
|