forked from OSchip/llvm-project
381 lines
14 KiB
LLVM
381 lines
14 KiB
LLVM
; RUN: opt < %s -disable-output "-passes=print<ddg>" 2>&1 | FileCheck %s
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; CHECK-LABEL: 'DDG' for loop 'test1.for.cond1.preheader':
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; CHECK: Node Address:[[N1:0x[0-9a-f]*]]:pi-block
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; CHECK-NEXT:--- start of nodes in pi-block ---
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; CHECK: Node Address:[[N2:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %j.02 = phi i64 [ %inc, %for.body4 ], [ 1, %for.body4.preheader ]
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N3:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N3]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %inc = add i64 %j.02, 1
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N2]]
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; CHECK-NEXT:--- end of nodes in pi-block ---
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N4:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N5:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N6:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N7:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N5]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %sub7 = add i64 %j.02, -1
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N8:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N9:0x[0-9a-f]*]]:pi-block
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; CHECK-NEXT:--- start of nodes in pi-block ---
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; CHECK: Node Address:[[N10:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %i.04 = phi i64 [ %inc13, %for.inc12 ], [ 0, %test1.for.cond1.preheader.preheader ]
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N11:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N11]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %inc13 = add i64 %i.04, 1
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N10]]
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; CHECK-NEXT:--- end of nodes in pi-block ---
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N12:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N13:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N14:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N15:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N15]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %exitcond = icmp ne i64 %inc13, %n
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; CHECK-NEXT: br i1 %exitcond, label %test1.for.cond1.preheader, label %for.end14.loopexit
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; CHECK-NEXT: Edges:none!
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; CHECK: Node Address:[[N14]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %4 = mul nsw i64 %i.04, %n
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; CHECK-NEXT: %arrayidx10 = getelementptr inbounds float, float* %a, i64 %4
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N6]]
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; CHECK: Node Address:[[N6]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %arrayidx11 = getelementptr inbounds float, float* %arrayidx10, i64 %j.02
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N18:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N13]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %2 = mul nsw i64 %i.04, %n
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; CHECK-NEXT: %arrayidx6 = getelementptr inbounds float, float* %a, i64 %2
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N8]]
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; CHECK: Node Address:[[N8]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %arrayidx8 = getelementptr inbounds float, float* %arrayidx6, i64 %sub7
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N18]]
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; CHECK: Node Address:[[N12]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %0 = mul nsw i64 %i.04, %n
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; CHECK-NEXT: %arrayidx = getelementptr inbounds float, float* %b, i64 %0
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N4]]
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; CHECK: Node Address:[[N4]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %arrayidx5 = getelementptr inbounds float, float* %arrayidx, i64 %j.02
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; CHECK-NEXT: %1 = load float, float* %arrayidx5, align 4
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N18]]
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; CHECK: Node Address:[[N18]]:pi-block
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; CHECK-NEXT:--- start of nodes in pi-block ---
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; CHECK: Node Address:[[N22:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %3 = load float, float* %arrayidx8, align 4
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N23:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N23]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %add = fadd float %1, %3
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N24:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N24]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: store float %add, float* %arrayidx11, align 4
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [memory] to [[N22]]
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; CHECK-NEXT:--- end of nodes in pi-block ---
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; CHECK-NEXT: Edges:none!
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; CHECK: Node Address:[[N25:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: br label %for.inc12
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; CHECK-NEXT: Edges:none!
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; CHECK: Node Address:[[N26:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: br label %for.body4
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; CHECK-NEXT: Edges:none!
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; CHECK: Node Address:[[N27:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %sub = add i64 %n, -1
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N7]]
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; CHECK-NEXT: [def-use] to [[N28:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N28]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %cmp21 = icmp ult i64 1, %sub
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; CHECK-NEXT: br i1 %cmp21, label %for.body4.preheader, label %for.inc12
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; CHECK-NEXT: Edges:none!
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; CHECK: Node Address:[[N7]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %cmp2 = icmp ult i64 %inc, %sub
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; CHECK-NEXT: br i1 %cmp2, label %for.body4, label %for.inc12.loopexit
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; CHECK-NEXT: Edges:none!
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;; This test has a cycle.
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;; void test1(unsigned long n, float a[][n], float b[][n]) {
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;; for (unsigned long i = 0; i < n; i++)
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;; for (unsigned long j = 1; j < n-1; j++)
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;; a[i][j] = b[i][j] + a[i][j-1];
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;; }
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define void @test1(i64 %n, float* noalias %a, float* noalias %b) {
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entry:
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%exitcond3 = icmp ne i64 0, %n
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br i1 %exitcond3, label %test1.for.cond1.preheader, label %for.end14
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test1.for.cond1.preheader: ; preds = %entry, %for.inc12
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%i.04 = phi i64 [ %inc13, %for.inc12 ], [ 0, %entry ]
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%sub = add i64 %n, -1
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%cmp21 = icmp ult i64 1, %sub
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br i1 %cmp21, label %for.body4, label %for.inc12
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for.body4: ; preds = %test1.for.cond1.preheader, %for.body4
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%j.02 = phi i64 [ %inc, %for.body4 ], [ 1, %test1.for.cond1.preheader ]
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%0 = mul nsw i64 %i.04, %n
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%arrayidx = getelementptr inbounds float, float* %b, i64 %0
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%arrayidx5 = getelementptr inbounds float, float* %arrayidx, i64 %j.02
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%1 = load float, float* %arrayidx5, align 4
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%2 = mul nsw i64 %i.04, %n
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%arrayidx6 = getelementptr inbounds float, float* %a, i64 %2
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%sub7 = add i64 %j.02, -1
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%arrayidx8 = getelementptr inbounds float, float* %arrayidx6, i64 %sub7
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%3 = load float, float* %arrayidx8, align 4
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%add = fadd float %1, %3
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%4 = mul nsw i64 %i.04, %n
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%arrayidx10 = getelementptr inbounds float, float* %a, i64 %4
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%arrayidx11 = getelementptr inbounds float, float* %arrayidx10, i64 %j.02
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store float %add, float* %arrayidx11, align 4
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%inc = add i64 %j.02, 1
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%cmp2 = icmp ult i64 %inc, %sub
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br i1 %cmp2, label %for.body4, label %for.inc12
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for.inc12: ; preds = %for.body4, %test1.for.cond1.preheader
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%inc13 = add i64 %i.04, 1
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%exitcond = icmp ne i64 %inc13, %n
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br i1 %exitcond, label %test1.for.cond1.preheader, label %for.end14
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for.end14: ; preds = %for.inc12, %entry
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ret void
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}
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; CHECK-LABEL: 'DDG' for loop 'test2.for.cond1.preheader':
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; CHECK: Node Address:[[PI1:0x[0-9a-f]*]]:pi-block
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; CHECK-NEXT:--- start of nodes in pi-block ---
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; CHECK: Node Address:[[N1:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %j.02 = phi i64 [ %inc, %for.body4 ], [ 1, %for.body4.preheader ]
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N2:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N2]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %inc = add i64 %j.02, 1
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N1]]
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; CHECK-NEXT:--- end of nodes in pi-block ---
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N3:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N4:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N5:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N6:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N4]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %add7 = add i64 %j.02, 1
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N7:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N8:0x[0-9a-f]*]]:pi-block
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; CHECK-NEXT:--- start of nodes in pi-block ---
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; CHECK: Node Address:[[N9:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %i.04 = phi i64 [ %inc13, %for.inc12 ], [ 0, %test2.for.cond1.preheader.preheader ]
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N10:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N10]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %inc13 = add i64 %i.04, 1
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N9]]
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; CHECK-NEXT:--- end of nodes in pi-block ---
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N11:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N12:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N13:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N14:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N14]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %exitcond = icmp ne i64 %inc13, %n
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; CHECK-NEXT: br i1 %exitcond, label %test2.for.cond1.preheader, label %for.end14.loopexit
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; CHECK-NEXT: Edges:none!
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; CHECK: Node Address:[[N13]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %4 = mul nsw i64 %i.04, %n
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; CHECK-NEXT: %arrayidx10 = getelementptr inbounds float, float* %a, i64 %4
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N5]]
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; CHECK: Node Address:[[N5]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %arrayidx11 = getelementptr inbounds float, float* %arrayidx10, i64 %j.02
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N17:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N12]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %2 = mul nsw i64 %i.04, %n
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; CHECK-NEXT: %arrayidx6 = getelementptr inbounds float, float* %a, i64 %2
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N7]]
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; CHECK: Node Address:[[N7]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %arrayidx8 = getelementptr inbounds float, float* %arrayidx6, i64 %add7
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; CHECK-NEXT: %3 = load float, float* %arrayidx8, align 4
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N20:0x[0-9a-f]*]]
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; CHECK-NEXT: [memory] to [[N17]]
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; CHECK: Node Address:[[N11]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %0 = mul nsw i64 %i.04, %n
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; CHECK-NEXT: %arrayidx = getelementptr inbounds float, float* %b, i64 %0
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N3]]
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; CHECK: Node Address:[[N3]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %arrayidx5 = getelementptr inbounds float, float* %arrayidx, i64 %j.02
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; CHECK-NEXT: %1 = load float, float* %arrayidx5, align 4
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N20]]
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; CHECK: Node Address:[[N20]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %add = fadd float %1, %3
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N17]]
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; CHECK: Node Address:[[N17]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: store float %add, float* %arrayidx11, align 4
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; CHECK-NEXT: Edges:none!
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; CHECK: Node Address:[[N23:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: br label %for.inc12
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; CHECK-NEXT: Edges:none!
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; CHECK: Node Address:[[N24:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: br label %for.body4
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; CHECK-NEXT: Edges:none!
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; CHECK: Node Address:[[N25:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %sub = add i64 %n, -1
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N6]]
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; CHECK-NEXT: [def-use] to [[N26:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N26]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %cmp21 = icmp ult i64 1, %sub
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; CHECK-NEXT: br i1 %cmp21, label %for.body4.preheader, label %for.inc12
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; CHECK-NEXT: Edges:none!
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; CHECK: Node Address:[[N6]]:multi-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %cmp2 = icmp ult i64 %inc, %sub
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; CHECK-NEXT: br i1 %cmp2, label %for.body4, label %for.inc12.loopexit
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; CHECK-NEXT: Edges:none!
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;; This test has no cycles.
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;; void test2(unsigned long n, float a[][n], float b[][n]) {
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;; for (unsigned long i = 0; i < n; i++)
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;; for (unsigned long j = 1; j < n-1; j++)
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;; a[i][j] = b[i][j] + a[i][j+1];
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;; }
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define void @test2(i64 %n, float* noalias %a, float* noalias %b) {
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entry:
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%exitcond3 = icmp ne i64 0, %n
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br i1 %exitcond3, label %test2.for.cond1.preheader, label %for.end14
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test2.for.cond1.preheader: ; preds = %entry, %for.inc12
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%i.04 = phi i64 [ %inc13, %for.inc12 ], [ 0, %entry ]
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%sub = add i64 %n, -1
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%cmp21 = icmp ult i64 1, %sub
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br i1 %cmp21, label %for.body4, label %for.inc12
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for.body4: ; preds = %test2.for.cond1.preheader, %for.body4
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%j.02 = phi i64 [ %inc, %for.body4 ], [ 1, %test2.for.cond1.preheader ]
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%0 = mul nsw i64 %i.04, %n
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%arrayidx = getelementptr inbounds float, float* %b, i64 %0
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%arrayidx5 = getelementptr inbounds float, float* %arrayidx, i64 %j.02
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%1 = load float, float* %arrayidx5, align 4
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%2 = mul nsw i64 %i.04, %n
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%arrayidx6 = getelementptr inbounds float, float* %a, i64 %2
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%add7 = add i64 %j.02, 1
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%arrayidx8 = getelementptr inbounds float, float* %arrayidx6, i64 %add7
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%3 = load float, float* %arrayidx8, align 4
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%add = fadd float %1, %3
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%4 = mul nsw i64 %i.04, %n
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%arrayidx10 = getelementptr inbounds float, float* %a, i64 %4
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%arrayidx11 = getelementptr inbounds float, float* %arrayidx10, i64 %j.02
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store float %add, float* %arrayidx11, align 4
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%inc = add i64 %j.02, 1
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%cmp2 = icmp ult i64 %inc, %sub
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br i1 %cmp2, label %for.body4, label %for.inc12
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for.inc12: ; preds = %for.body4, %test2.for.cond1.preheader
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%inc13 = add i64 %i.04, 1
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%exitcond = icmp ne i64 %inc13, %n
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br i1 %exitcond, label %test2.for.cond1.preheader, label %for.end14
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|
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for.end14: ; preds = %for.inc12, %entry
|
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ret void
|
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} |