forked from OSchip/llvm-project
271 lines
8.4 KiB
C++
271 lines
8.4 KiB
C++
//===-- WebAssemblyUtilities.cpp - WebAssembly Utility Functions ----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements several utility functions for WebAssembly.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyUtilities.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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using namespace llvm;
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const char *const WebAssembly::ClangCallTerminateFn = "__clang_call_terminate";
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const char *const WebAssembly::CxaBeginCatchFn = "__cxa_begin_catch";
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const char *const WebAssembly::CxaRethrowFn = "__cxa_rethrow";
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const char *const WebAssembly::StdTerminateFn = "_ZSt9terminatev";
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const char *const WebAssembly::PersonalityWrapperFn =
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"_Unwind_Wasm_CallPersonality";
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bool WebAssembly::isArgument(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::ARGUMENT_i32:
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case WebAssembly::ARGUMENT_i32_S:
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case WebAssembly::ARGUMENT_i64:
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case WebAssembly::ARGUMENT_i64_S:
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case WebAssembly::ARGUMENT_f32:
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case WebAssembly::ARGUMENT_f32_S:
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case WebAssembly::ARGUMENT_f64:
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case WebAssembly::ARGUMENT_f64_S:
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case WebAssembly::ARGUMENT_v16i8:
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case WebAssembly::ARGUMENT_v16i8_S:
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case WebAssembly::ARGUMENT_v8i16:
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case WebAssembly::ARGUMENT_v8i16_S:
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case WebAssembly::ARGUMENT_v4i32:
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case WebAssembly::ARGUMENT_v4i32_S:
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case WebAssembly::ARGUMENT_v2i64:
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case WebAssembly::ARGUMENT_v2i64_S:
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case WebAssembly::ARGUMENT_v4f32:
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case WebAssembly::ARGUMENT_v4f32_S:
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case WebAssembly::ARGUMENT_v2f64:
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case WebAssembly::ARGUMENT_v2f64_S:
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return true;
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default:
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return false;
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}
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}
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bool WebAssembly::isCopy(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::COPY_I32:
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case WebAssembly::COPY_I32_S:
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case WebAssembly::COPY_I64:
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case WebAssembly::COPY_I64_S:
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case WebAssembly::COPY_F32:
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case WebAssembly::COPY_F32_S:
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case WebAssembly::COPY_F64:
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case WebAssembly::COPY_F64_S:
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case WebAssembly::COPY_V128:
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case WebAssembly::COPY_V128_S:
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return true;
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default:
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return false;
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}
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}
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bool WebAssembly::isTee(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::TEE_I32:
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case WebAssembly::TEE_I32_S:
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case WebAssembly::TEE_I64:
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case WebAssembly::TEE_I64_S:
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case WebAssembly::TEE_F32:
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case WebAssembly::TEE_F32_S:
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case WebAssembly::TEE_F64:
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case WebAssembly::TEE_F64_S:
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case WebAssembly::TEE_V128:
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case WebAssembly::TEE_V128_S:
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return true;
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default:
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return false;
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}
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}
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/// Test whether MI is a child of some other node in an expression tree.
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bool WebAssembly::isChild(const MachineInstr &MI,
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const WebAssemblyFunctionInfo &MFI) {
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if (MI.getNumOperands() == 0)
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return false;
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const MachineOperand &MO = MI.getOperand(0);
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if (!MO.isReg() || MO.isImplicit() || !MO.isDef())
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return false;
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unsigned Reg = MO.getReg();
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return TargetRegisterInfo::isVirtualRegister(Reg) &&
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MFI.isVRegStackified(Reg);
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}
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bool WebAssembly::isCallDirect(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::CALL_VOID:
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case WebAssembly::CALL_VOID_S:
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case WebAssembly::CALL_I32:
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case WebAssembly::CALL_I32_S:
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case WebAssembly::CALL_I64:
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case WebAssembly::CALL_I64_S:
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case WebAssembly::CALL_F32:
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case WebAssembly::CALL_F32_S:
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case WebAssembly::CALL_F64:
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case WebAssembly::CALL_F64_S:
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case WebAssembly::CALL_v16i8:
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case WebAssembly::CALL_v16i8_S:
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case WebAssembly::CALL_v8i16:
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case WebAssembly::CALL_v8i16_S:
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case WebAssembly::CALL_v4i32:
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case WebAssembly::CALL_v4i32_S:
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case WebAssembly::CALL_v2i64:
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case WebAssembly::CALL_v2i64_S:
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case WebAssembly::CALL_v4f32:
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case WebAssembly::CALL_v4f32_S:
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case WebAssembly::CALL_v2f64:
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case WebAssembly::CALL_v2f64_S:
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case WebAssembly::CALL_EXCEPT_REF:
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case WebAssembly::CALL_EXCEPT_REF_S:
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return true;
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default:
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return false;
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}
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}
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bool WebAssembly::isCallIndirect(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::CALL_INDIRECT_VOID:
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case WebAssembly::CALL_INDIRECT_VOID_S:
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case WebAssembly::CALL_INDIRECT_I32:
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case WebAssembly::CALL_INDIRECT_I32_S:
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case WebAssembly::CALL_INDIRECT_I64:
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case WebAssembly::CALL_INDIRECT_I64_S:
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case WebAssembly::CALL_INDIRECT_F32:
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case WebAssembly::CALL_INDIRECT_F32_S:
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case WebAssembly::CALL_INDIRECT_F64:
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case WebAssembly::CALL_INDIRECT_F64_S:
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case WebAssembly::CALL_INDIRECT_v16i8:
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case WebAssembly::CALL_INDIRECT_v16i8_S:
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case WebAssembly::CALL_INDIRECT_v8i16:
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case WebAssembly::CALL_INDIRECT_v8i16_S:
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case WebAssembly::CALL_INDIRECT_v4i32:
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case WebAssembly::CALL_INDIRECT_v4i32_S:
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case WebAssembly::CALL_INDIRECT_v2i64:
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case WebAssembly::CALL_INDIRECT_v2i64_S:
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case WebAssembly::CALL_INDIRECT_v4f32:
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case WebAssembly::CALL_INDIRECT_v4f32_S:
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case WebAssembly::CALL_INDIRECT_v2f64:
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case WebAssembly::CALL_INDIRECT_v2f64_S:
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case WebAssembly::CALL_INDIRECT_EXCEPT_REF:
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case WebAssembly::CALL_INDIRECT_EXCEPT_REF_S:
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return true;
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default:
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return false;
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}
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}
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unsigned WebAssembly::getCalleeOpNo(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::CALL_VOID:
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case WebAssembly::CALL_VOID_S:
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case WebAssembly::CALL_INDIRECT_VOID:
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case WebAssembly::CALL_INDIRECT_VOID_S:
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return 0;
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case WebAssembly::CALL_I32:
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case WebAssembly::CALL_I32_S:
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case WebAssembly::CALL_I64:
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case WebAssembly::CALL_I64_S:
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case WebAssembly::CALL_F32:
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case WebAssembly::CALL_F32_S:
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case WebAssembly::CALL_F64:
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case WebAssembly::CALL_F64_S:
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case WebAssembly::CALL_v16i8:
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case WebAssembly::CALL_v16i8_S:
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case WebAssembly::CALL_v8i16:
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case WebAssembly::CALL_v8i16_S:
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case WebAssembly::CALL_v4i32:
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case WebAssembly::CALL_v4i32_S:
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case WebAssembly::CALL_v2i64:
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case WebAssembly::CALL_v2i64_S:
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case WebAssembly::CALL_v4f32:
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case WebAssembly::CALL_v4f32_S:
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case WebAssembly::CALL_v2f64:
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case WebAssembly::CALL_v2f64_S:
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case WebAssembly::CALL_EXCEPT_REF:
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case WebAssembly::CALL_EXCEPT_REF_S:
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case WebAssembly::CALL_INDIRECT_I32:
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case WebAssembly::CALL_INDIRECT_I32_S:
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case WebAssembly::CALL_INDIRECT_I64:
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case WebAssembly::CALL_INDIRECT_I64_S:
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case WebAssembly::CALL_INDIRECT_F32:
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case WebAssembly::CALL_INDIRECT_F32_S:
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case WebAssembly::CALL_INDIRECT_F64:
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case WebAssembly::CALL_INDIRECT_F64_S:
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case WebAssembly::CALL_INDIRECT_v16i8:
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case WebAssembly::CALL_INDIRECT_v16i8_S:
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case WebAssembly::CALL_INDIRECT_v8i16:
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case WebAssembly::CALL_INDIRECT_v8i16_S:
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case WebAssembly::CALL_INDIRECT_v4i32:
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case WebAssembly::CALL_INDIRECT_v4i32_S:
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case WebAssembly::CALL_INDIRECT_v2i64:
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case WebAssembly::CALL_INDIRECT_v2i64_S:
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case WebAssembly::CALL_INDIRECT_v4f32:
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case WebAssembly::CALL_INDIRECT_v4f32_S:
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case WebAssembly::CALL_INDIRECT_v2f64:
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case WebAssembly::CALL_INDIRECT_v2f64_S:
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case WebAssembly::CALL_INDIRECT_EXCEPT_REF:
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case WebAssembly::CALL_INDIRECT_EXCEPT_REF_S:
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return 1;
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default:
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llvm_unreachable("Not a call instruction");
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}
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}
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bool WebAssembly::isMarker(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::BLOCK:
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case WebAssembly::BLOCK_S:
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case WebAssembly::END_BLOCK:
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case WebAssembly::END_BLOCK_S:
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case WebAssembly::LOOP:
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case WebAssembly::LOOP_S:
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case WebAssembly::END_LOOP:
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case WebAssembly::END_LOOP_S:
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case WebAssembly::TRY:
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case WebAssembly::TRY_S:
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case WebAssembly::END_TRY:
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case WebAssembly::END_TRY_S:
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return true;
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default:
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return false;
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}
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}
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bool WebAssembly::mayThrow(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::THROW:
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case WebAssembly::THROW_S:
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case WebAssembly::RETHROW:
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case WebAssembly::RETHROW_S:
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return true;
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}
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if (isCallIndirect(MI))
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return true;
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if (!MI.isCall())
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return false;
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const MachineOperand &MO = MI.getOperand(getCalleeOpNo(MI));
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assert(MO.isGlobal());
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const auto *F = dyn_cast<Function>(MO.getGlobal());
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if (!F)
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return true;
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if (F->doesNotThrow())
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return false;
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// These functions never throw
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if (F->getName() == CxaBeginCatchFn || F->getName() == PersonalityWrapperFn ||
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F->getName() == ClangCallTerminateFn || F->getName() == StdTerminateFn)
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return false;
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return true;
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}
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