llvm-project/llvm/test/CodeGen/Hexagon/autohvx
Sanjay Patel f24900b934 [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates
The transform performs a bitwise logic op in a wider type followed by
truncate when both inputs are truncated from the same source type:
logic_op (truncate x), (truncate y) --> truncate (logic_op x, y)

There are a bunch of other checks that should prevent doing this when 
it might be harmful.

We already do this transform for scalars in this spot. The vector 
limitation was shared with a check for the case when the operands are 
extended. I'm not sure if that limit is needed either, but that would 
be a separate patch.

Differential Revision: https://reviews.llvm.org/D55448

llvm-svn: 349303
2018-12-16 14:57:04 +00:00
..
align-64b.ll [Hexagon] Use vector align-left when shift amount fits in 3 bits 2018-05-30 13:45:34 +00:00
align-128b.ll [Hexagon] Use vector align-left when shift amount fits in 3 bits 2018-05-30 13:45:34 +00:00
align2-64b.ll [Hexagon] Use vector align-left when shift amount fits in 3 bits 2018-05-30 13:45:34 +00:00
align2-128b.ll [Hexagon] Use vector align-left when shift amount fits in 3 bits 2018-05-30 13:45:34 +00:00
arith.ll
bitcount-64b.ll [Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZ 2018-06-01 14:52:58 +00:00
bitcount-128b.ll [Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZ 2018-06-01 14:52:58 +00:00
bitwise-pred-64b.ll [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates 2018-12-16 14:57:04 +00:00
bitwise-pred-128b.ll [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates 2018-12-16 14:57:04 +00:00
bswap.ll
build-vector-i32-type.ll [Hexagon] make test immune to improvements in undef simplification 2018-11-19 15:34:09 +00:00
concat-vectors-64b.ll
concat-vectors-128b.ll
contract-64b.ll
contract-128b.ll
ctpop-split.ll [Hexagon] Split CTPOP of vector pairs 2018-06-06 18:03:29 +00:00
deal-64b.ll
deal-128b.ll
delta-64b.ll
delta-128b.ll
delta2-64b.ll
extract-element.ll
float-cost.ll [Hexagon] Make floating point operations expensive for vectorization 2018-06-12 15:12:50 +00:00
interleave.ll [Hexagon] Enable interleaving in loop vectorizer 2018-08-22 20:15:04 +00:00
isel-anyext-inreg.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-anyext-pair.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-bitcast-vsplat.ll
isel-bitcast-vsplat2.ll
isel-bool-vector.ll
isel-build-undef.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-concat-multiple.ll [Hexagon] make test immune to scalarization improvements; NFC 2018-12-14 17:23:01 +00:00
isel-concat-vectors-bool.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-concat-vectors.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-const-splat-bitcast.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-const-splat.ll
isel-const-vector.ll
isel-expand-unaligned-loads-noindexed.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-expand-unaligned-loads.ll
isel-extractelt-illegal-type.ll DAG combiner: fold (select, C, X, undef) -> X 2018-11-16 23:13:38 +00:00
isel-qfalse.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-select-const.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-setcc-pair.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-sext-inreg.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-shift-byte.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-shuffle-gather.ll [Hexagon] Use shuffles when lowering "gather" shufflevectors 2018-09-12 22:14:52 +00:00
isel-shuffle-pack.ll
isel-truncate.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-vec-ext.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
isel-vsplat-pair.ll [Hexagon] Simplify CFG after atomic expansion 2018-08-02 22:17:53 +00:00
lower-insert-elt.ll
maximize-bandwidth.ll
perfect-single.ll
reg-sequence.ll
shift-64b.ll
shift-128b.ll
shuff-64b.ll
shuff-128b.ll
shuff-combos-64b.ll
shuff-combos-128b.ll
shuff-single.ll
vdd0.ll [Hexagon] Implement vector-pair zero as V6_vsubw_dv 2018-06-06 19:34:40 +00:00
vector-compare-64b.ll
vector-compare-128b.ll
vext-64b.ll
vext-128b.ll
vmux-order.ll