forked from OSchip/llvm-project
299 lines
11 KiB
C++
299 lines
11 KiB
C++
//===- ARCDisassembler.cpp - Disassembler for ARC ---------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file is part of the ARC Disassembler.
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///
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//===----------------------------------------------------------------------===//
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#include "ARC.h"
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#include "ARCRegisterInfo.h"
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#include "MCTargetDesc/ARCMCTargetDesc.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "arc-disassembler"
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using DecodeStatus = MCDisassembler::DecodeStatus;
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namespace {
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/// \brief A disassembler class for ARC.
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class ARCDisassembler : public MCDisassembler {
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public:
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std::unique_ptr<MCInstrInfo const> const MCII;
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ARCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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MCInstrInfo const *MCII)
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: MCDisassembler(STI, Ctx), MCII(MCII) {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const override;
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};
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} // end anonymous namespace
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static bool readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint32_t &Insn) {
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Size = 4;
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// Read 2 16-bit values, but swap hi/lo parts.
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Insn =
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(Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) | (Bytes[3] << 8);
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return true;
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}
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static bool readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint64_t &Insn) {
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Size = 8;
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Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) |
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((uint64_t)Bytes[2] << 0) | ((uint64_t)Bytes[3] << 8) |
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((uint64_t)Bytes[4] << 48) | ((uint64_t)Bytes[5] << 56) |
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((uint64_t)Bytes[6] << 32) | ((uint64_t)Bytes[7] << 40);
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return true;
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}
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static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint32_t &Insn) {
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Size = 2;
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Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
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return true;
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}
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static MCDisassembler::DecodeStatus DecodeS12Operand(MCInst &, unsigned,
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uint64_t, const void *);
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static MCDisassembler::DecodeStatus DecodeS9Operand(MCInst &, unsigned,
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uint64_t, const void *);
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static MCDisassembler::DecodeStatus
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DecodeBranchTargetS9(MCInst &, unsigned, uint64_t, const void *);
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static MCDisassembler::DecodeStatus
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DecodeBranchTargetS21(MCInst &, unsigned, uint64_t, const void *);
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static MCDisassembler::DecodeStatus
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DecodeBranchTargetS25(MCInst &, unsigned, uint64_t, const void *);
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static MCDisassembler::DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t,
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const void *);
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static MCDisassembler::DecodeStatus
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DecodeLdLImmInstruction(MCInst &, uint64_t, uint64_t, const void *);
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static MCDisassembler::DecodeStatus
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DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t, const void *);
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static MCDisassembler::DecodeStatus
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DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t, const void *);
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static const uint16_t GPR32DecoderTable[] = {
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ARC::R0, ARC::R1, ARC::R2, ARC::R3, ARC::R4, ARC::R5, ARC::R6,
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ARC::R7, ARC::R8, ARC::R9, ARC::R10, ARC::R11, ARC::R12, ARC::R13,
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ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,
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ARC::R21, ARC::R22, ARC::R23, ARC::R24, ARC::R25, ARC::GP, ARC::FP,
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ARC::SP, ARC::ILINK, ARC::R30, ARC::BLINK};
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static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= 32) {
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DEBUG(dbgs() << "Not a GPR32 register.");
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return MCDisassembler::Fail;
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}
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unsigned Reg = GPR32DecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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#include "ARCGenDisassemblerTables.inc"
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static unsigned decodeCField(unsigned Insn) {
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return fieldFromInstruction(Insn, 6, 6);
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}
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static unsigned decodeBField(unsigned Insn) {
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return (fieldFromInstruction(Insn, 12, 3) << 3) |
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fieldFromInstruction(Insn, 24, 3);
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}
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static unsigned decodeAField(unsigned Insn) {
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return fieldFromInstruction(Insn, 0, 6);
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}
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static MCDisassembler::DecodeStatus
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DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Dec) {
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// We have the 9-bit immediate in the low bits, 6-bit register in high bits.
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unsigned S9 = Insn & 0x1ff;
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unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9;
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DecodeGPR32RegisterClass(Inst, R, Address, Dec);
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Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S9)));
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return MCDisassembler::Success;
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}
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static MCDisassembler::DecodeStatus DecodeS9Operand(MCInst &Inst,
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unsigned InsnS9,
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uint64_t Address,
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const void *Decoder) {
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Inst.addOperand(MCOperand::createImm(SignExtend32<9>(0x1ff & InsnS9)));
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return MCDisassembler::Success;
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}
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static MCDisassembler::DecodeStatus DecodeS12Operand(MCInst &Inst,
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unsigned InsnS12,
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uint64_t Address,
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const void *Decoder) {
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Inst.addOperand(MCOperand::createImm(SignExtend32<12>(0xfff & InsnS12)));
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return MCDisassembler::Success;
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}
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static MCDisassembler::DecodeStatus DecodeBranchTargetS9(MCInst &Inst,
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unsigned S,
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uint64_t Address,
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const void *Decoder) {
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Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S)));
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return MCDisassembler::Success;
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}
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static MCDisassembler::DecodeStatus DecodeBranchTargetS21(MCInst &Inst,
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unsigned S,
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uint64_t Address,
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const void *Decoder) {
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Inst.addOperand(MCOperand::createImm(SignExtend32<21>(S)));
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return MCDisassembler::Success;
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}
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static MCDisassembler::DecodeStatus DecodeBranchTargetS25(MCInst &Inst,
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unsigned S,
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uint64_t Address,
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const void *Decoder) {
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Inst.addOperand(MCOperand::createImm(SignExtend32<25>(S)));
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return MCDisassembler::Success;
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}
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static MCDisassembler::DecodeStatus
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DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address,
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const void *Decoder) {
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unsigned SrcC, DstB, LImm;
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DstB = decodeBField(Insn);
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if (DstB != 62) {
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DEBUG(dbgs() << "Decoding StLImm found non-limm register.");
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return MCDisassembler::Fail;
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}
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SrcC = decodeCField(Insn);
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DecodeGPR32RegisterClass(Inst, SrcC, Address, Decoder);
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LImm = (Insn >> 32);
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Inst.addOperand(MCOperand::createImm(LImm));
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Inst.addOperand(MCOperand::createImm(0));
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return MCDisassembler::Success;
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}
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static MCDisassembler::DecodeStatus
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DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address,
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const void *Decoder) {
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unsigned DstA, SrcB, LImm;
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DEBUG(dbgs() << "Decoding LdLImm:\n");
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SrcB = decodeBField(Insn);
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if (SrcB != 62) {
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DEBUG(dbgs() << "Decoding LdLImm found non-limm register.");
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return MCDisassembler::Fail;
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}
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DstA = decodeAField(Insn);
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DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder);
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LImm = (Insn >> 32);
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Inst.addOperand(MCOperand::createImm(LImm));
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Inst.addOperand(MCOperand::createImm(0));
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return MCDisassembler::Success;
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}
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static MCDisassembler::DecodeStatus
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DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address,
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const void *Decoder) {
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unsigned DstA, SrcB;
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DEBUG(dbgs() << "Decoding LdRLimm\n");
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DstA = decodeAField(Insn);
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DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder);
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SrcB = decodeBField(Insn);
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DecodeGPR32RegisterClass(Inst, SrcB, Address, Decoder);
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if (decodeCField(Insn) != 62) {
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DEBUG(dbgs() << "Decoding LdRLimm found non-limm register.");
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return MCDisassembler::Fail;
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}
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Inst.addOperand(MCOperand::createImm((uint32_t)(Insn >> 32)));
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return MCDisassembler::Success;
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}
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MCDisassembler::DecodeStatus ARCDisassembler::getInstruction(
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MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &vStream, raw_ostream &cStream) const {
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MCDisassembler::DecodeStatus Result;
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if (Bytes.size() < 2) {
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Size = 0;
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return Fail;
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}
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uint8_t DecodeByte = (Bytes[1] & 0xF7) >> 3;
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// 0x00 -> 0x07 are 32-bit instructions.
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// 0x08 -> 0x1F are 16-bit instructions.
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if (DecodeByte < 0x08) {
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// 32-bit instruction.
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if (Bytes.size() < 4) {
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// Did we decode garbage?
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Size = 0;
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return Fail;
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}
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if (Bytes.size() >= 8) {
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// Attempt to decode 64-bit instruction.
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uint64_t Insn64;
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if (!readInstruction64(Bytes, Address, Size, Insn64))
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return Fail;
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Result =
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decodeInstruction(DecoderTable64, Instr, Insn64, Address, this, STI);
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if (Result == MCDisassembler::Success) {
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DEBUG(dbgs() << "Successfully decoded 64-bit instruction.");
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return MCDisassembler::Success;
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}
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DEBUG(dbgs() << "Not a 64-bit instruction, falling back to 32-bit.");
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}
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uint32_t Insn32;
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if (!readInstruction32(Bytes, Address, Size, Insn32)) {
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return Fail;
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}
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// Calling the auto-generated decoder function.
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return decodeInstruction(DecoderTable32, Instr, Insn32, Address, this, STI);
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}
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// 16-bit instruction.
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uint32_t Insn16;
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if (!readInstruction16(Bytes, Address, Size, Insn16)) {
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return Fail;
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}
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// Calling the auto-generated decoder function.
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return decodeInstruction(DecoderTable16, Instr, Insn16, Address, this, STI);
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}
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static MCDisassembler *createARCDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new ARCDisassembler(STI, Ctx, T.createMCInstrInfo());
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}
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extern "C" void LLVMInitializeARCDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(getTheARCTarget(),
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createARCDisassembler);
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}
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