forked from OSchip/llvm-project
193 lines
6.3 KiB
C++
193 lines
6.3 KiB
C++
//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Hexagon target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonTargetMachine.h"
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#include "Hexagon.h"
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#include "HexagonISelLowering.h"
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#include "HexagonMachineScheduler.h"
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#include "HexagonTargetObjectFile.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Transforms/IPO/PassManagerBuilder.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
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cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
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static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon CFG Optimization"));
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static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
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cl::init(true), cl::Hidden, cl::ZeroOrMore,
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cl::desc("Early expansion of MUX"));
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static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
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cl::Hidden, cl::desc("Generate \"insert\" instructions"));
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/// HexagonTargetMachineModule - Note that this is used on hosts that
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/// cannot link in a library unless there are references into the
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/// library. In particular, it seems that it is not possible to get
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/// things to work on Win32 without this. Though it is unused, do not
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/// remove it.
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extern "C" int HexagonTargetMachineModule;
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int HexagonTargetMachineModule = 0;
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extern "C" void LLVMInitializeHexagonTarget() {
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// Register the target.
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RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
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}
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static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
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return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
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}
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static MachineSchedRegistry
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SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
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createVLIWMachineSched);
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namespace llvm {
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FunctionPass *createHexagonExpandCondsets();
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FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createHexagonDelaySlotFillerPass(const TargetMachine &TM);
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FunctionPass *createHexagonRemoveExtendArgs(const HexagonTargetMachine &TM);
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FunctionPass *createHexagonCFGOptimizer();
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FunctionPass *createHexagonSplitConst32AndConst64();
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FunctionPass *createHexagonExpandPredSpillCode();
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FunctionPass *createHexagonGenInsert();
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FunctionPass *createHexagonHardwareLoops();
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FunctionPass *createHexagonPeephole();
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FunctionPass *createHexagonFixupHwLoops();
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FunctionPass *createHexagonNewValueJump();
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FunctionPass *createHexagonCopyToCombine();
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FunctionPass *createHexagonPacketizer();
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FunctionPass *createHexagonNewValueJump();
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} // end namespace llvm;
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/// HexagonTargetMachine ctor - Create an ILP32 architecture model.
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///
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/// Hexagon_TODO: Do I need an aggregate alignment?
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///
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HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
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Options, RM, CM, OL),
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TLOF(make_unique<HexagonTargetObjectFile>()),
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Subtarget(TT, CPU, FS, *this) {
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initAsmInfo();
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}
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HexagonTargetMachine::~HexagonTargetMachine() {}
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namespace {
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/// Hexagon Code Generator Pass Configuration Options.
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class HexagonPassConfig : public TargetPassConfig {
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public:
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HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {
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bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None);
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if (!NoOpt) {
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if (EnableExpandCondsets) {
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Pass *Exp = createHexagonExpandCondsets();
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insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
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}
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}
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}
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HexagonTargetMachine &getHexagonTargetMachine() const {
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return getTM<HexagonTargetMachine>();
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}
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ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const override {
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return createVLIWMachineSched(C);
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}
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bool addInstSelector() override;
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void addPreRegAlloc() override;
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void addPostRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new HexagonPassConfig(this, PM);
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}
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bool HexagonPassConfig::addInstSelector() {
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HexagonTargetMachine &TM = getHexagonTargetMachine();
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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if (!NoOpt)
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addPass(createHexagonRemoveExtendArgs(TM));
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addPass(createHexagonISelDag(TM, getOptLevel()));
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if (!NoOpt) {
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addPass(createHexagonPeephole());
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printAndVerify("After hexagon peephole pass");
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if (EnableGenInsert)
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addPass(createHexagonGenInsert(), false);
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}
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return false;
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}
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void HexagonPassConfig::addPreRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None)
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if (!DisableHardwareLoops)
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addPass(createHexagonHardwareLoops(), false);
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}
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void HexagonPassConfig::addPostRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None)
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if (!DisableHexagonCFGOpt)
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addPass(createHexagonCFGOptimizer(), false);
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}
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void HexagonPassConfig::addPreSched2() {
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addPass(createHexagonCopyToCombine(), false);
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if (getOptLevel() != CodeGenOpt::None)
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addPass(&IfConverterID, false);
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addPass(createHexagonSplitConst32AndConst64());
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}
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void HexagonPassConfig::addPreEmitPass() {
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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if (!NoOpt)
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addPass(createHexagonNewValueJump(), false);
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// Expand Spill code for predicate registers.
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addPass(createHexagonExpandPredSpillCode(), false);
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// Create Packets.
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if (!NoOpt) {
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if (!DisableHardwareLoops)
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addPass(createHexagonFixupHwLoops(), false);
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addPass(createHexagonPacketizer(), false);
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}
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}
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