forked from OSchip/llvm-project
151 lines
5.6 KiB
ArmAsm
151 lines
5.6 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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lsl z18.b, z28.b, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
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// CHECK-NEXT: lsl z18.b, z28.b, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z1.b, z9.b, #8
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
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// CHECK-NEXT: lsl z1.b, z9.b, #8
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z18.b, p0/m, z28.b, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
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// CHECK-NEXT: lsl z18.b, p0/m, z28.b, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z1.b, p0/m, z9.b, #8
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
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// CHECK-NEXT: lsl z1.b, p0/m, z9.b, #8
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z21.h, z2.h, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
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// CHECK-NEXT: lsl z21.h, z2.h, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z14.h, z30.h, #16
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
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// CHECK-NEXT: lsl z14.h, z30.h, #16
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z21.h, p0/m, z2.h, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
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// CHECK-NEXT: lsl z21.h, p0/m, z2.h, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z14.h, p0/m, z30.h, #16
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
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// CHECK-NEXT: lsl z14.h, p0/m, z30.h, #16
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z6.s, z12.s, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
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// CHECK-NEXT: lsl z6.s, z12.s, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z23.s, z19.s, #32
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
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// CHECK-NEXT: lsl z23.s, z19.s, #32
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z6.s, p0/m, z12.s, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
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// CHECK-NEXT: lsl z6.s, p0/m, z12.s, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z23.s, p0/m, z19.s, #32
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
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// CHECK-NEXT: lsl z23.s, p0/m, z19.s, #32
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z3.d, z24.d, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
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// CHECK-NEXT: lsl z3.d, z24.d, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z25.d, z16.d, #64
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
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// CHECK-NEXT: lsl z25.d, z16.d, #64
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z3.d, p0/m, z24.d, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
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// CHECK-NEXT: lsl z3.d, p0/m, z24.d, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z25.d, p0/m, z16.d, #64
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
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// CHECK-NEXT: lsl z25.d, p0/m, z16.d, #64
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Source and Destination Registers must match
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lsl z0.b, p0/m, z1.b, z2.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: lsl z0.b, p0/m, z1.b, z2.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z0.b, p0/m, z1.b, #1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: lsl z0.b, p0/m, z1.b, #1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Element sizes must match
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lsl z0.b, z0.d, z1.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: lsl z0.b, z0.d, z1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z0.b, p0/m, z0.d, z1.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: lsl z0.b, p0/m, z0.d, z1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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lsl z0.b, p0/m, z0.b, z1.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Predicate not in restricted predicate range
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lsl z0.b, p8/m, z0.b, z1.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: lsl z0.b, p8/m, z0.b, z1.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p0/z, z6.d
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lsl z31.d, z31.d, #63
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: lsl z31.d, z31.d, #63
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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lsl z31.d, z31.d, #63
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: lsl z31.d, z31.d, #63
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0.s, p0/z, z7.s
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lsl z0.s, z1.s, z2.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: lsl z0.s, z1.s, z2.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0, z7
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lsl z0.s, z1.s, z2.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: lsl z0.s, z1.s, z2.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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