forked from OSchip/llvm-project
98 lines
3.9 KiB
ArmAsm
98 lines
3.9 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate out of lower bound [-128, 112].
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ld1rqw z0.s, p0/z, [x0, #-144]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112].
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// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, #-144]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rqw z0.s, p0/z, [x0, #-129]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112].
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// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, #-129]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rqw z0.s, p0/z, [x0, #113]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112].
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// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, #113]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rqw z0.s, p0/z, [x0, #128]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112].
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// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, #128]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rqw z0.s, p0/z, [x0, #12]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 16 in range [-128, 112].
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// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, #12]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid immediate suffix
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ld1rqw z0.s, p0/z, [x0, #16, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, #16, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid destination register width.
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ld1rqw z0.b, p0/z, [x0, x1, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ld1rqw z0.b, p0/z, [x0, x1, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rqw z0.h, p0/z, [x0, x1, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ld1rqw z0.h, p0/z, [x0, x1, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rqw z0.d, p0/z, [x0, x1, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ld1rqw z0.d, p0/z, [x0, x1, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
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ld1rqw z0.s, p0/z, [x0, xzr, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, xzr, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rqw z0.s, p0/z, [x0, x1, lsl #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, x1, lsl #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rqw z0.s, p0/z, [x0, w1, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, w1, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rqw z0.s, p0/z, [x0, w1, uxtw #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, w1, uxtw #1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z23.s, p3/z, z30.s
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ld1rqw { z23.s }, p3/z, [x13, #112]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld1rqw { z23.s }, p3/z, [x13, #112]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z23, z30
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ld1rqw { z23.s }, p3/z, [x13, #112]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld1rqw { z23.s }, p3/z, [x13, #112]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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