forked from OSchip/llvm-project
74 lines
2.8 KiB
ArmAsm
74 lines
2.8 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid immediate (multiple of 4 in range [0, 252]).
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ld1rd z0.d, p1/z, [x0, #-8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 504].
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// CHECK-NEXT: ld1rd z0.d, p1/z, [x0, #-8]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rd z0.d, p1/z, [x0, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 504].
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// CHECK-NEXT: ld1rd z0.d, p1/z, [x0, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rd z0.d, p1/z, [x0, #505]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 504].
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// CHECK-NEXT: ld1rd z0.d, p1/z, [x0, #505]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rd z0.d, p1/z, [x0, #512]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 504].
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// CHECK-NEXT: ld1rd z0.d, p1/z, [x0, #512]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rd z0.d, p1/z, [x0, #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 504].
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// CHECK-NEXT: ld1rd z0.d, p1/z, [x0, #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid result vector element size
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ld1rd z0.b, p1/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ld1rd z0.b, p1/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rd z0.h, p1/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ld1rd z0.h, p1/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rd z0.s, p1/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ld1rd z0.s, p1/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// restricted predicate has range [0, 7].
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ld1rd z0.d, p8/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: ld1rd z0.d, p8/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p7/z, z6.d
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ld1rd { z31.d }, p7/z, [sp, #504]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld1rd { z31.d }, p7/z, [sp, #504]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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ld1rd { z31.d }, p7/z, [sp, #504]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld1rd { z31.d }, p7/z, [sp, #504]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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