forked from OSchip/llvm-project
1105 lines
34 KiB
C++
1105 lines
34 KiB
C++
//===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief R600 Implementation of TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "R600InstrInfo.h"
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDGPUTargetMachine.h"
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#include "R600Defines.h"
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#include "R600MachineFunctionInfo.h"
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#include "R600RegisterInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#define GET_INSTRINFO_CTOR
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#include "AMDGPUGenDFAPacketizer.inc"
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using namespace llvm;
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R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
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: AMDGPUInstrInfo(tm),
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RI(tm, *this),
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ST(tm.getSubtarget<AMDGPUSubtarget>())
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{ }
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const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
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return RI;
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}
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bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
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return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
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}
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bool R600InstrInfo::isVector(const MachineInstr &MI) const {
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return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
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}
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void
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R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
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&& AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
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for (unsigned I = 0; I < 4; I++) {
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unsigned SubRegIndex = RI.getSubRegFromChannel(I);
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buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
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RI.getSubReg(DestReg, SubRegIndex),
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RI.getSubReg(SrcReg, SubRegIndex))
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.addReg(DestReg,
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RegState::Define | RegState::Implicit);
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}
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} else {
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// We can't copy vec4 registers
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assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
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&& !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
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MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
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DestReg, SrcReg);
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NewMI->getOperand(getOperandIdx(*NewMI, R600Operands::SRC0))
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.setIsKill(KillSrc);
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}
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}
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MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
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unsigned DstReg, int64_t Imm) const {
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MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
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MachineInstrBuilder MIB(*MF, MI);
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MIB.addReg(DstReg, RegState::Define);
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MIB.addReg(AMDGPU::ALU_LITERAL_X);
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MIB.addImm(Imm);
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MIB.addReg(0); // PREDICATE_BIT
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return MI;
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}
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unsigned R600InstrInfo::getIEQOpcode() const {
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return AMDGPU::SETE_INT;
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}
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bool R600InstrInfo::isMov(unsigned Opcode) const {
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switch(Opcode) {
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default: return false;
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case AMDGPU::MOV:
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case AMDGPU::MOV_IMM_F32:
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case AMDGPU::MOV_IMM_I32:
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return true;
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}
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}
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// Some instructions act as place holders to emulate operations that the GPU
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// hardware does automatically. This function can be used to check if
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// an opcode falls into this category.
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bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
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switch (Opcode) {
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default: return false;
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case AMDGPU::RETURN:
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return true;
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}
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}
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bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
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switch(Opcode) {
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default: return false;
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}
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}
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bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
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switch(Opcode) {
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default: return false;
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case AMDGPU::CUBE_r600_pseudo:
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case AMDGPU::CUBE_r600_real:
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case AMDGPU::CUBE_eg_pseudo:
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case AMDGPU::CUBE_eg_real:
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return true;
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}
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}
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bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
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unsigned TargetFlags = get(Opcode).TSFlags;
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return ((TargetFlags & R600_InstFlag::OP1) |
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(TargetFlags & R600_InstFlag::OP2) |
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(TargetFlags & R600_InstFlag::OP3));
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}
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bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
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return (get(Opcode).TSFlags & R600_InstFlag::TRANS_ONLY);
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}
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bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
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return isTransOnly(MI->getOpcode());
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}
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bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
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return ST.hasVertexCache() && IS_VTX(get(Opcode));
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}
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bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
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const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
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return MFI->ShaderType != ShaderType::COMPUTE && usesVertexCache(MI->getOpcode());
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}
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bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
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return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
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}
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bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
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const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
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return (MFI->ShaderType == ShaderType::COMPUTE && usesVertexCache(MI->getOpcode())) ||
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usesTextureCache(MI->getOpcode());
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}
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SmallVector<std::pair<MachineOperand *, int64_t>, 3>
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R600InstrInfo::getSrcs(MachineInstr *MI) const {
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SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
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static const R600Operands::Ops OpTable[3][2] = {
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{R600Operands::SRC0, R600Operands::SRC0_SEL},
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{R600Operands::SRC1, R600Operands::SRC1_SEL},
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{R600Operands::SRC2, R600Operands::SRC2_SEL},
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};
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for (unsigned j = 0; j < 3; j++) {
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int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
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if (SrcIdx < 0)
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break;
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MachineOperand &MO = MI->getOperand(SrcIdx);
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unsigned Reg = MI->getOperand(SrcIdx).getReg();
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if (Reg == AMDGPU::ALU_CONST) {
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unsigned Sel = MI->getOperand(
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getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
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Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
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continue;
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}
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if (Reg == AMDGPU::ALU_LITERAL_X) {
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unsigned Imm = MI->getOperand(
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getOperandIdx(MI->getOpcode(), R600Operands::IMM)).getImm();
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Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Imm));
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continue;
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}
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Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, 0));
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}
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return Result;
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}
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std::vector<std::pair<int, unsigned> >
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R600InstrInfo::ExtractSrcs(MachineInstr *MI,
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const DenseMap<unsigned, unsigned> &PV)
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const {
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const SmallVector<std::pair<MachineOperand *, int64_t>, 3> Srcs = getSrcs(MI);
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const std::pair<int, unsigned> DummyPair(-1, 0);
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std::vector<std::pair<int, unsigned> > Result;
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unsigned i = 0;
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for (unsigned n = Srcs.size(); i < n; ++i) {
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unsigned Reg = Srcs[i].first->getReg();
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unsigned Index = RI.getEncodingValue(Reg) & 0xff;
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unsigned Chan = RI.getHWRegChan(Reg);
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if (Index > 127) {
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Result.push_back(DummyPair);
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continue;
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}
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if (PV.find(Index) != PV.end()) {
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Result.push_back(DummyPair);
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continue;
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}
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Result.push_back(std::pair<int, unsigned>(Index, Chan));
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}
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for (; i < 3; ++i)
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Result.push_back(DummyPair);
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return Result;
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}
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static std::vector<std::pair<int, unsigned> >
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Swizzle(std::vector<std::pair<int, unsigned> > Src,
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R600InstrInfo::BankSwizzle Swz) {
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switch (Swz) {
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case R600InstrInfo::ALU_VEC_012:
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break;
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case R600InstrInfo::ALU_VEC_021:
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std::swap(Src[1], Src[2]);
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break;
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case R600InstrInfo::ALU_VEC_102:
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std::swap(Src[0], Src[1]);
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break;
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case R600InstrInfo::ALU_VEC_120:
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std::swap(Src[0], Src[1]);
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std::swap(Src[0], Src[2]);
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break;
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case R600InstrInfo::ALU_VEC_201:
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std::swap(Src[0], Src[2]);
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std::swap(Src[0], Src[1]);
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break;
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case R600InstrInfo::ALU_VEC_210:
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std::swap(Src[0], Src[2]);
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break;
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}
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return Src;
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}
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static bool
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isLegal(const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
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const std::vector<R600InstrInfo::BankSwizzle> &Swz,
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unsigned CheckedSize) {
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int Vector[4][3];
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memset(Vector, -1, sizeof(Vector));
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for (unsigned i = 0; i < CheckedSize; i++) {
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const std::vector<std::pair<int, unsigned> > &Srcs =
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Swizzle(IGSrcs[i], Swz[i]);
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for (unsigned j = 0; j < 3; j++) {
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const std::pair<int, unsigned> &Src = Srcs[j];
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if (Src.first < 0)
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continue;
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if (Vector[Src.second][j] < 0)
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Vector[Src.second][j] = Src.first;
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if (Vector[Src.second][j] != Src.first)
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return false;
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}
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}
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return true;
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}
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static bool recursiveFitsFPLimitation(
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const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
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std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
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unsigned Depth = 0) {
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if (!isLegal(IGSrcs, SwzCandidate, Depth))
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return false;
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if (IGSrcs.size() == Depth)
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return true;
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unsigned i = SwzCandidate[Depth];
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for (; i < 6; i++) {
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SwzCandidate[Depth] = (R600InstrInfo::BankSwizzle) i;
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if (recursiveFitsFPLimitation(IGSrcs, SwzCandidate, Depth + 1))
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return true;
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}
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SwzCandidate[Depth] = R600InstrInfo::ALU_VEC_012;
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return false;
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}
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bool
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R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
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const DenseMap<unsigned, unsigned> &PV,
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std::vector<BankSwizzle> &ValidSwizzle)
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const {
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//Todo : support shared src0 - src1 operand
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std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
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ValidSwizzle.clear();
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for (unsigned i = 0, e = IG.size(); i < e; ++i) {
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IGSrcs.push_back(ExtractSrcs(IG[i], PV));
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unsigned Op = getOperandIdx(IG[i]->getOpcode(),
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R600Operands::BANK_SWIZZLE);
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ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
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IG[i]->getOperand(Op).getImm());
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}
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bool Result = recursiveFitsFPLimitation(IGSrcs, ValidSwizzle);
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if (!Result)
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return false;
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return true;
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}
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bool
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R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
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const {
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assert (Consts.size() <= 12 && "Too many operands in instructions group");
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unsigned Pair1 = 0, Pair2 = 0;
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for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
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unsigned ReadConstHalf = Consts[i] & 2;
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unsigned ReadConstIndex = Consts[i] & (~3);
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unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
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if (!Pair1) {
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Pair1 = ReadHalfConst;
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continue;
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}
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if (Pair1 == ReadHalfConst)
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continue;
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if (!Pair2) {
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Pair2 = ReadHalfConst;
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continue;
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}
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if (Pair2 != ReadHalfConst)
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return false;
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}
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return true;
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}
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bool
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R600InstrInfo::canBundle(const std::vector<MachineInstr *> &MIs) const {
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std::vector<unsigned> Consts;
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for (unsigned i = 0, n = MIs.size(); i < n; i++) {
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MachineInstr *MI = MIs[i];
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if (!isALUInstr(MI->getOpcode()))
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continue;
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const SmallVector<std::pair<MachineOperand *, int64_t>, 3> &Srcs =
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getSrcs(MI);
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for (unsigned j = 0, e = Srcs.size(); j < e; j++) {
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std::pair<MachineOperand *, unsigned> Src = Srcs[j];
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if (Src.first->getReg() == AMDGPU::ALU_CONST)
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Consts.push_back(Src.second);
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if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
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AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
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unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
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unsigned Chan = RI.getHWRegChan(Src.first->getReg());
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Consts.push_back((Index << 2) | Chan);
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}
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}
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}
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return fitsConstReadLimitations(Consts);
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}
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DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
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const ScheduleDAG *DAG) const {
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const InstrItineraryData *II = TM->getInstrItineraryData();
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return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
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}
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static bool
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isPredicateSetter(unsigned Opcode) {
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switch (Opcode) {
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case AMDGPU::PRED_X:
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return true;
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default:
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return false;
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}
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}
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static MachineInstr *
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findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) {
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while (I != MBB.begin()) {
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--I;
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MachineInstr *MI = I;
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if (isPredicateSetter(MI->getOpcode()))
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return MI;
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}
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return NULL;
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}
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static
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bool isJump(unsigned Opcode) {
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return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
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}
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bool
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R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// Most of the following comes from the ARM implementation of AnalyzeBranch
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin())
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return false;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return false;
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--I;
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}
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if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
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return false;
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}
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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unsigned LastOpc = LastInst->getOpcode();
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if (I == MBB.begin() ||
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!isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
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if (LastOpc == AMDGPU::JUMP) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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} else if (LastOpc == AMDGPU::JUMP_COND) {
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MachineInstr *predSet = I;
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while (!isPredicateSetter(predSet->getOpcode())) {
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predSet = --I;
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}
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TBB = LastInst->getOperand(0).getMBB();
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Cond.push_back(predSet->getOperand(1));
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Cond.push_back(predSet->getOperand(2));
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Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
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return false;
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}
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return true; // Can't handle indirect branch.
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}
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// Get the instruction before it if it is a terminator.
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MachineInstr *SecondLastInst = I;
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unsigned SecondLastOpc = SecondLastInst->getOpcode();
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// If the block ends with a B and a Bcc, handle it.
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if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
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MachineInstr *predSet = --I;
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while (!isPredicateSetter(predSet->getOpcode())) {
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predSet = --I;
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}
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TBB = SecondLastInst->getOperand(0).getMBB();
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FBB = LastInst->getOperand(0).getMBB();
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Cond.push_back(predSet->getOperand(1));
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Cond.push_back(predSet->getOperand(2));
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Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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int R600InstrInfo::getBranchInstr(const MachineOperand &op) const {
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const MachineInstr *MI = op.getParent();
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switch (MI->getDesc().OpInfo->RegClass) {
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default: // FIXME: fallthrough??
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case AMDGPU::GPRI32RegClassID: return AMDGPU::BRANCH_COND_i32;
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case AMDGPU::GPRF32RegClassID: return AMDGPU::BRANCH_COND_f32;
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};
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}
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unsigned
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R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
|
|
DebugLoc DL) const {
|
|
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
|
|
|
if (FBB == 0) {
|
|
if (Cond.empty()) {
|
|
BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
|
|
return 1;
|
|
} else {
|
|
MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
|
|
assert(PredSet && "No previous predicate !");
|
|
addFlag(PredSet, 0, MO_FLAG_PUSH);
|
|
PredSet->getOperand(2).setImm(Cond[1].getImm());
|
|
|
|
BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
|
|
.addMBB(TBB)
|
|
.addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
|
|
return 1;
|
|
}
|
|
} else {
|
|
MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
|
|
assert(PredSet && "No previous predicate !");
|
|
addFlag(PredSet, 0, MO_FLAG_PUSH);
|
|
PredSet->getOperand(2).setImm(Cond[1].getImm());
|
|
BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
|
|
.addMBB(TBB)
|
|
.addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
|
|
BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
|
|
return 2;
|
|
}
|
|
}
|
|
|
|
unsigned
|
|
R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
|
|
|
// Note : we leave PRED* instructions there.
|
|
// They may be needed when predicating instructions.
|
|
|
|
MachineBasicBlock::iterator I = MBB.end();
|
|
|
|
if (I == MBB.begin()) {
|
|
return 0;
|
|
}
|
|
--I;
|
|
switch (I->getOpcode()) {
|
|
default:
|
|
return 0;
|
|
case AMDGPU::JUMP_COND: {
|
|
MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
|
|
clearFlag(predSet, 0, MO_FLAG_PUSH);
|
|
I->eraseFromParent();
|
|
break;
|
|
}
|
|
case AMDGPU::JUMP:
|
|
I->eraseFromParent();
|
|
break;
|
|
}
|
|
I = MBB.end();
|
|
|
|
if (I == MBB.begin()) {
|
|
return 1;
|
|
}
|
|
--I;
|
|
switch (I->getOpcode()) {
|
|
// FIXME: only one case??
|
|
default:
|
|
return 1;
|
|
case AMDGPU::JUMP_COND: {
|
|
MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
|
|
clearFlag(predSet, 0, MO_FLAG_PUSH);
|
|
I->eraseFromParent();
|
|
break;
|
|
}
|
|
case AMDGPU::JUMP:
|
|
I->eraseFromParent();
|
|
break;
|
|
}
|
|
return 2;
|
|
}
|
|
|
|
bool
|
|
R600InstrInfo::isPredicated(const MachineInstr *MI) const {
|
|
int idx = MI->findFirstPredOperandIdx();
|
|
if (idx < 0)
|
|
return false;
|
|
|
|
unsigned Reg = MI->getOperand(idx).getReg();
|
|
switch (Reg) {
|
|
default: return false;
|
|
case AMDGPU::PRED_SEL_ONE:
|
|
case AMDGPU::PRED_SEL_ZERO:
|
|
case AMDGPU::PREDICATE_BIT:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
bool
|
|
R600InstrInfo::isPredicable(MachineInstr *MI) const {
|
|
// XXX: KILL* instructions can be predicated, but they must be the last
|
|
// instruction in a clause, so this means any instructions after them cannot
|
|
// be predicated. Until we have proper support for instruction clauses in the
|
|
// backend, we will mark KILL* instructions as unpredicable.
|
|
|
|
if (MI->getOpcode() == AMDGPU::KILLGT) {
|
|
return false;
|
|
} else if (isVector(*MI)) {
|
|
return false;
|
|
} else {
|
|
return AMDGPUInstrInfo::isPredicable(MI);
|
|
}
|
|
}
|
|
|
|
|
|
bool
|
|
R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
|
|
unsigned NumCyles,
|
|
unsigned ExtraPredCycles,
|
|
const BranchProbability &Probability) const{
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
|
|
unsigned NumTCycles,
|
|
unsigned ExtraTCycles,
|
|
MachineBasicBlock &FMBB,
|
|
unsigned NumFCycles,
|
|
unsigned ExtraFCycles,
|
|
const BranchProbability &Probability) const {
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
|
|
unsigned NumCyles,
|
|
const BranchProbability &Probability)
|
|
const {
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
|
|
MachineBasicBlock &FMBB) const {
|
|
return false;
|
|
}
|
|
|
|
|
|
bool
|
|
R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
|
|
MachineOperand &MO = Cond[1];
|
|
switch (MO.getImm()) {
|
|
case OPCODE_IS_ZERO_INT:
|
|
MO.setImm(OPCODE_IS_NOT_ZERO_INT);
|
|
break;
|
|
case OPCODE_IS_NOT_ZERO_INT:
|
|
MO.setImm(OPCODE_IS_ZERO_INT);
|
|
break;
|
|
case OPCODE_IS_ZERO:
|
|
MO.setImm(OPCODE_IS_NOT_ZERO);
|
|
break;
|
|
case OPCODE_IS_NOT_ZERO:
|
|
MO.setImm(OPCODE_IS_ZERO);
|
|
break;
|
|
default:
|
|
return true;
|
|
}
|
|
|
|
MachineOperand &MO2 = Cond[2];
|
|
switch (MO2.getReg()) {
|
|
case AMDGPU::PRED_SEL_ZERO:
|
|
MO2.setReg(AMDGPU::PRED_SEL_ONE);
|
|
break;
|
|
case AMDGPU::PRED_SEL_ONE:
|
|
MO2.setReg(AMDGPU::PRED_SEL_ZERO);
|
|
break;
|
|
default:
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool
|
|
R600InstrInfo::DefinesPredicate(MachineInstr *MI,
|
|
std::vector<MachineOperand> &Pred) const {
|
|
return isPredicateSetter(MI->getOpcode());
|
|
}
|
|
|
|
|
|
bool
|
|
R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
|
|
const SmallVectorImpl<MachineOperand> &Pred2) const {
|
|
return false;
|
|
}
|
|
|
|
|
|
bool
|
|
R600InstrInfo::PredicateInstruction(MachineInstr *MI,
|
|
const SmallVectorImpl<MachineOperand> &Pred) const {
|
|
int PIdx = MI->findFirstPredOperandIdx();
|
|
|
|
if (PIdx != -1) {
|
|
MachineOperand &PMO = MI->getOperand(PIdx);
|
|
PMO.setReg(Pred[2].getReg());
|
|
MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
|
|
MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
|
|
const MachineInstr *MI,
|
|
unsigned *PredCost) const {
|
|
if (PredCost)
|
|
*PredCost = 2;
|
|
return 2;
|
|
}
|
|
|
|
int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
|
|
const MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
int Offset = 0;
|
|
|
|
if (MFI->getNumObjects() == 0) {
|
|
return -1;
|
|
}
|
|
|
|
if (MRI.livein_empty()) {
|
|
return 0;
|
|
}
|
|
|
|
for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
|
|
LE = MRI.livein_end();
|
|
LI != LE; ++LI) {
|
|
Offset = std::max(Offset,
|
|
GET_REG_INDEX(RI.getEncodingValue(LI->first)));
|
|
}
|
|
|
|
return Offset + 1;
|
|
}
|
|
|
|
int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
|
|
int Offset = 0;
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
// Variable sized objects are not supported
|
|
assert(!MFI->hasVarSizedObjects());
|
|
|
|
if (MFI->getNumObjects() == 0) {
|
|
return -1;
|
|
}
|
|
|
|
Offset = TM.getFrameLowering()->getFrameIndexOffset(MF, -1);
|
|
|
|
return getIndirectIndexBegin(MF) + Offset;
|
|
}
|
|
|
|
std::vector<unsigned> R600InstrInfo::getIndirectReservedRegs(
|
|
const MachineFunction &MF) const {
|
|
const AMDGPUFrameLowering *TFL =
|
|
static_cast<const AMDGPUFrameLowering*>(TM.getFrameLowering());
|
|
std::vector<unsigned> Regs;
|
|
|
|
unsigned StackWidth = TFL->getStackWidth(MF);
|
|
int End = getIndirectIndexEnd(MF);
|
|
|
|
if (End == -1) {
|
|
return Regs;
|
|
}
|
|
|
|
for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
|
|
unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
|
|
Regs.push_back(SuperReg);
|
|
for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
|
|
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
|
|
Regs.push_back(Reg);
|
|
}
|
|
}
|
|
return Regs;
|
|
}
|
|
|
|
unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
|
|
unsigned Channel) const {
|
|
// XXX: Remove when we support a stack width > 2
|
|
assert(Channel == 0);
|
|
return RegIndex;
|
|
}
|
|
|
|
const TargetRegisterClass * R600InstrInfo::getIndirectAddrStoreRegClass(
|
|
unsigned SourceReg) const {
|
|
return &AMDGPU::R600_TReg32RegClass;
|
|
}
|
|
|
|
const TargetRegisterClass *R600InstrInfo::getIndirectAddrLoadRegClass() const {
|
|
return &AMDGPU::TRegMemRegClass;
|
|
}
|
|
|
|
MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned ValueReg, unsigned Address,
|
|
unsigned OffsetReg) const {
|
|
unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
|
|
MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
|
|
AMDGPU::AR_X, OffsetReg);
|
|
setImmOperand(MOVA, R600Operands::WRITE, 0);
|
|
|
|
MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
|
|
AddrReg, ValueReg)
|
|
.addReg(AMDGPU::AR_X, RegState::Implicit);
|
|
setImmOperand(Mov, R600Operands::DST_REL, 1);
|
|
return Mov;
|
|
}
|
|
|
|
MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned ValueReg, unsigned Address,
|
|
unsigned OffsetReg) const {
|
|
unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
|
|
MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
|
|
AMDGPU::AR_X,
|
|
OffsetReg);
|
|
setImmOperand(MOVA, R600Operands::WRITE, 0);
|
|
MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
|
|
ValueReg,
|
|
AddrReg)
|
|
.addReg(AMDGPU::AR_X, RegState::Implicit);
|
|
setImmOperand(Mov, R600Operands::SRC0_REL, 1);
|
|
|
|
return Mov;
|
|
}
|
|
|
|
const TargetRegisterClass *R600InstrInfo::getSuperIndirectRegClass() const {
|
|
return &AMDGPU::IndirectRegRegClass;
|
|
}
|
|
|
|
unsigned R600InstrInfo::getMaxAlusPerClause() const {
|
|
return 115;
|
|
}
|
|
|
|
MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned Opcode,
|
|
unsigned DstReg,
|
|
unsigned Src0Reg,
|
|
unsigned Src1Reg) const {
|
|
MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
|
|
DstReg); // $dst
|
|
|
|
if (Src1Reg) {
|
|
MIB.addImm(0) // $update_exec_mask
|
|
.addImm(0); // $update_predicate
|
|
}
|
|
MIB.addImm(1) // $write
|
|
.addImm(0) // $omod
|
|
.addImm(0) // $dst_rel
|
|
.addImm(0) // $dst_clamp
|
|
.addReg(Src0Reg) // $src0
|
|
.addImm(0) // $src0_neg
|
|
.addImm(0) // $src0_rel
|
|
.addImm(0) // $src0_abs
|
|
.addImm(-1); // $src0_sel
|
|
|
|
if (Src1Reg) {
|
|
MIB.addReg(Src1Reg) // $src1
|
|
.addImm(0) // $src1_neg
|
|
.addImm(0) // $src1_rel
|
|
.addImm(0) // $src1_abs
|
|
.addImm(-1); // $src1_sel
|
|
}
|
|
|
|
//XXX: The r600g finalizer expects this to be 1, once we've moved the
|
|
//scheduling to the backend, we can change the default to 0.
|
|
MIB.addImm(1) // $last
|
|
.addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
|
|
.addImm(0) // $literal
|
|
.addImm(0); // $bank_swizzle
|
|
|
|
return MIB;
|
|
}
|
|
|
|
#define OPERAND_CASE(Label) \
|
|
case Label: { \
|
|
static const R600Operands::VecOps Ops[] = \
|
|
{ \
|
|
Label##_X, \
|
|
Label##_Y, \
|
|
Label##_Z, \
|
|
Label##_W \
|
|
}; \
|
|
return Ops[Slot]; \
|
|
}
|
|
|
|
static R600Operands::VecOps
|
|
getSlotedOps(R600Operands::Ops Op, unsigned Slot) {
|
|
switch (Op) {
|
|
OPERAND_CASE(R600Operands::UPDATE_EXEC_MASK)
|
|
OPERAND_CASE(R600Operands::UPDATE_PREDICATE)
|
|
OPERAND_CASE(R600Operands::WRITE)
|
|
OPERAND_CASE(R600Operands::OMOD)
|
|
OPERAND_CASE(R600Operands::DST_REL)
|
|
OPERAND_CASE(R600Operands::CLAMP)
|
|
OPERAND_CASE(R600Operands::SRC0)
|
|
OPERAND_CASE(R600Operands::SRC0_NEG)
|
|
OPERAND_CASE(R600Operands::SRC0_REL)
|
|
OPERAND_CASE(R600Operands::SRC0_ABS)
|
|
OPERAND_CASE(R600Operands::SRC0_SEL)
|
|
OPERAND_CASE(R600Operands::SRC1)
|
|
OPERAND_CASE(R600Operands::SRC1_NEG)
|
|
OPERAND_CASE(R600Operands::SRC1_REL)
|
|
OPERAND_CASE(R600Operands::SRC1_ABS)
|
|
OPERAND_CASE(R600Operands::SRC1_SEL)
|
|
OPERAND_CASE(R600Operands::PRED_SEL)
|
|
default:
|
|
llvm_unreachable("Wrong Operand");
|
|
}
|
|
}
|
|
|
|
#undef OPERAND_CASE
|
|
|
|
static int
|
|
getVecOperandIdx(R600Operands::VecOps Op) {
|
|
return 1 + Op;
|
|
}
|
|
|
|
|
|
MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
|
|
MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
|
|
const {
|
|
assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
|
|
unsigned Opcode;
|
|
const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
|
|
if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD4XXX)
|
|
Opcode = AMDGPU::DOT4_r600;
|
|
else
|
|
Opcode = AMDGPU::DOT4_eg;
|
|
MachineBasicBlock::iterator I = MI;
|
|
MachineOperand &Src0 = MI->getOperand(
|
|
getVecOperandIdx(getSlotedOps(R600Operands::SRC0, Slot)));
|
|
MachineOperand &Src1 = MI->getOperand(
|
|
getVecOperandIdx(getSlotedOps(R600Operands::SRC1, Slot)));
|
|
MachineInstr *MIB = buildDefaultInstruction(
|
|
MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
|
|
static const R600Operands::Ops Operands[14] = {
|
|
R600Operands::UPDATE_EXEC_MASK,
|
|
R600Operands::UPDATE_PREDICATE,
|
|
R600Operands::WRITE,
|
|
R600Operands::OMOD,
|
|
R600Operands::DST_REL,
|
|
R600Operands::CLAMP,
|
|
R600Operands::SRC0_NEG,
|
|
R600Operands::SRC0_REL,
|
|
R600Operands::SRC0_ABS,
|
|
R600Operands::SRC0_SEL,
|
|
R600Operands::SRC1_NEG,
|
|
R600Operands::SRC1_REL,
|
|
R600Operands::SRC1_ABS,
|
|
R600Operands::SRC1_SEL,
|
|
};
|
|
|
|
for (unsigned i = 0; i < 14; i++) {
|
|
MachineOperand &MO = MI->getOperand(
|
|
getVecOperandIdx(getSlotedOps(Operands[i], Slot)));
|
|
assert (MO.isImm());
|
|
setImmOperand(MIB, Operands[i], MO.getImm());
|
|
}
|
|
MIB->getOperand(20).setImm(0);
|
|
return MIB;
|
|
}
|
|
|
|
MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned DstReg,
|
|
uint64_t Imm) const {
|
|
MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
|
|
AMDGPU::ALU_LITERAL_X);
|
|
setImmOperand(MovImm, R600Operands::IMM, Imm);
|
|
return MovImm;
|
|
}
|
|
|
|
int R600InstrInfo::getOperandIdx(const MachineInstr &MI,
|
|
R600Operands::Ops Op) const {
|
|
return getOperandIdx(MI.getOpcode(), Op);
|
|
}
|
|
|
|
int R600InstrInfo::getOperandIdx(unsigned Opcode,
|
|
R600Operands::Ops Op) const {
|
|
unsigned TargetFlags = get(Opcode).TSFlags;
|
|
unsigned OpTableIdx;
|
|
|
|
if (!HAS_NATIVE_OPERANDS(TargetFlags)) {
|
|
switch (Op) {
|
|
case R600Operands::DST: return 0;
|
|
case R600Operands::SRC0: return 1;
|
|
case R600Operands::SRC1: return 2;
|
|
case R600Operands::SRC2: return 3;
|
|
default:
|
|
assert(!"Unknown operand type for instruction");
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
if (TargetFlags & R600_InstFlag::OP1) {
|
|
OpTableIdx = 0;
|
|
} else if (TargetFlags & R600_InstFlag::OP2) {
|
|
OpTableIdx = 1;
|
|
} else {
|
|
assert((TargetFlags & R600_InstFlag::OP3) && "OP1, OP2, or OP3 not defined "
|
|
"for this instruction");
|
|
OpTableIdx = 2;
|
|
}
|
|
|
|
return R600Operands::ALUOpTable[OpTableIdx][Op];
|
|
}
|
|
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void R600InstrInfo::setImmOperand(MachineInstr *MI, R600Operands::Ops Op,
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int64_t Imm) const {
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int Idx = getOperandIdx(*MI, Op);
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assert(Idx != -1 && "Operand not supported for this instruction.");
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assert(MI->getOperand(Idx).isImm());
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MI->getOperand(Idx).setImm(Imm);
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}
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//===----------------------------------------------------------------------===//
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// Instruction flag getters/setters
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//===----------------------------------------------------------------------===//
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bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
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return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
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}
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MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
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unsigned Flag) const {
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unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
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int FlagIndex = 0;
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if (Flag != 0) {
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// If we pass something other than the default value of Flag to this
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// function, it means we are want to set a flag on an instruction
|
|
// that uses native encoding.
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assert(HAS_NATIVE_OPERANDS(TargetFlags));
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bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
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|
switch (Flag) {
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case MO_FLAG_CLAMP:
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FlagIndex = getOperandIdx(*MI, R600Operands::CLAMP);
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|
break;
|
|
case MO_FLAG_MASK:
|
|
FlagIndex = getOperandIdx(*MI, R600Operands::WRITE);
|
|
break;
|
|
case MO_FLAG_NOT_LAST:
|
|
case MO_FLAG_LAST:
|
|
FlagIndex = getOperandIdx(*MI, R600Operands::LAST);
|
|
break;
|
|
case MO_FLAG_NEG:
|
|
switch (SrcIdx) {
|
|
case 0: FlagIndex = getOperandIdx(*MI, R600Operands::SRC0_NEG); break;
|
|
case 1: FlagIndex = getOperandIdx(*MI, R600Operands::SRC1_NEG); break;
|
|
case 2: FlagIndex = getOperandIdx(*MI, R600Operands::SRC2_NEG); break;
|
|
}
|
|
break;
|
|
|
|
case MO_FLAG_ABS:
|
|
assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
|
|
"instructions.");
|
|
(void)IsOP3;
|
|
switch (SrcIdx) {
|
|
case 0: FlagIndex = getOperandIdx(*MI, R600Operands::SRC0_ABS); break;
|
|
case 1: FlagIndex = getOperandIdx(*MI, R600Operands::SRC1_ABS); break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
FlagIndex = -1;
|
|
break;
|
|
}
|
|
assert(FlagIndex != -1 && "Flag not supported for this instruction");
|
|
} else {
|
|
FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
|
|
assert(FlagIndex != 0 &&
|
|
"Instruction flags not supported for this instruction");
|
|
}
|
|
|
|
MachineOperand &FlagOp = MI->getOperand(FlagIndex);
|
|
assert(FlagOp.isImm());
|
|
return FlagOp;
|
|
}
|
|
|
|
void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
|
|
unsigned Flag) const {
|
|
unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
|
|
if (Flag == 0) {
|
|
return;
|
|
}
|
|
if (HAS_NATIVE_OPERANDS(TargetFlags)) {
|
|
MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
|
|
if (Flag == MO_FLAG_NOT_LAST) {
|
|
clearFlag(MI, Operand, MO_FLAG_LAST);
|
|
} else if (Flag == MO_FLAG_MASK) {
|
|
clearFlag(MI, Operand, Flag);
|
|
} else {
|
|
FlagOp.setImm(1);
|
|
}
|
|
} else {
|
|
MachineOperand &FlagOp = getFlagOp(MI, Operand);
|
|
FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
|
|
}
|
|
}
|
|
|
|
void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
|
|
unsigned Flag) const {
|
|
unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
|
|
if (HAS_NATIVE_OPERANDS(TargetFlags)) {
|
|
MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
|
|
FlagOp.setImm(0);
|
|
} else {
|
|
MachineOperand &FlagOp = getFlagOp(MI);
|
|
unsigned InstFlags = FlagOp.getImm();
|
|
InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
|
|
FlagOp.setImm(InstFlags);
|
|
}
|
|
}
|