forked from OSchip/llvm-project
1402 lines
54 KiB
C++
1402 lines
54 KiB
C++
//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that X86 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
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#define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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namespace llvm {
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class X86Subtarget;
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class X86TargetMachine;
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namespace X86ISD {
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// X86 Specific DAG Nodes
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enum NodeType : unsigned {
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// Start the numbering where the builtin ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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/// Bit scan forward.
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BSF,
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/// Bit scan reverse.
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BSR,
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/// Double shift instructions. These correspond to
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/// X86::SHLDxx and X86::SHRDxx instructions.
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SHLD,
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SHRD,
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/// Bitwise logical AND of floating point values. This corresponds
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/// to X86::ANDPS or X86::ANDPD.
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FAND,
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/// Bitwise logical OR of floating point values. This corresponds
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/// to X86::ORPS or X86::ORPD.
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FOR,
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/// Bitwise logical XOR of floating point values. This corresponds
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/// to X86::XORPS or X86::XORPD.
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FXOR,
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/// Bitwise logical ANDNOT of floating point values. This
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/// corresponds to X86::ANDNPS or X86::ANDNPD.
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FANDN,
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/// These operations represent an abstract X86 call
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/// instruction, which includes a bunch of information. In particular the
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/// operands of these node are:
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///
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/// #0 - The incoming token chain
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/// #1 - The callee
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/// #2 - The number of arg bytes the caller pushes on the stack.
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/// #3 - The number of arg bytes the callee pops off the stack.
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/// #4 - The value to pass in AL/AX/EAX (optional)
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/// #5 - The value to pass in DL/DX/EDX (optional)
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///
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/// The result values of these nodes are:
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///
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/// #0 - The outgoing token chain
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/// #1 - The first register result value (optional)
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/// #2 - The second register result value (optional)
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///
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CALL,
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/// This operation implements the lowering for readcyclecounter.
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RDTSC_DAG,
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/// X86 Read Time-Stamp Counter and Processor ID.
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RDTSCP_DAG,
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/// X86 Read Performance Monitoring Counters.
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RDPMC_DAG,
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/// X86 compare and logical compare instructions.
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CMP, COMI, UCOMI,
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/// X86 bit-test instructions.
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BT,
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/// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
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/// operand, usually produced by a CMP instruction.
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SETCC,
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/// X86 Select
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SELECT, SELECTS,
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// Same as SETCC except it's materialized with a sbb and the value is all
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// one's or all zero's.
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SETCC_CARRY, // R = carry_bit ? ~0 : 0
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/// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
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/// Operands are two FP values to compare; result is a mask of
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/// 0s or 1s. Generally DTRT for C/C++ with NaNs.
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FSETCC,
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/// X86 FP SETCC, similar to above, but with output as an i1 mask and
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/// with optional rounding mode.
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FSETCCM, FSETCCM_RND,
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/// X86 conditional moves. Operand 0 and operand 1 are the two values
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/// to select from. Operand 2 is the condition code, and operand 3 is the
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/// flag operand produced by a CMP or TEST instruction. It also writes a
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/// flag result.
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CMOV,
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/// X86 conditional branches. Operand 0 is the chain operand, operand 1
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/// is the block to branch if condition is true, operand 2 is the
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/// condition code, and operand 3 is the flag operand produced by a CMP
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/// or TEST instruction.
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BRCOND,
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/// Return with a flag operand. Operand 0 is the chain operand, operand
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/// 1 is the number of bytes of stack to pop.
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RET_FLAG,
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/// Return from interrupt. Operand 0 is the number of bytes to pop.
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IRET,
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/// Repeat fill, corresponds to X86::REP_STOSx.
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REP_STOS,
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/// Repeat move, corresponds to X86::REP_MOVSx.
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REP_MOVS,
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/// On Darwin, this node represents the result of the popl
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/// at function entry, used for PIC code.
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GlobalBaseReg,
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/// A wrapper node for TargetConstantPool, TargetJumpTable,
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/// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress,
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/// MCSymbol and TargetBlockAddress.
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Wrapper,
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/// Special wrapper used under X86-64 PIC mode for RIP
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/// relative displacements.
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WrapperRIP,
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/// Copies a 64-bit value from the low word of an XMM vector
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/// to an MMX vector.
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MOVDQ2Q,
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/// Copies a 32-bit value from the low word of a MMX
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/// vector to a GPR.
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MMX_MOVD2W,
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/// Copies a GPR into the low 32-bit word of a MMX vector
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/// and zero out the high word.
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MMX_MOVW2D,
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/// Extract an 8-bit value from a vector and zero extend it to
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/// i32, corresponds to X86::PEXTRB.
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PEXTRB,
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/// Extract a 16-bit value from a vector and zero extend it to
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/// i32, corresponds to X86::PEXTRW.
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PEXTRW,
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/// Insert any element of a 4 x float vector into any element
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/// of a destination 4 x floatvector.
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INSERTPS,
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/// Insert the lower 8-bits of a 32-bit value to a vector,
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/// corresponds to X86::PINSRB.
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PINSRB,
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/// Insert the lower 16-bits of a 32-bit value to a vector,
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/// corresponds to X86::PINSRW.
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PINSRW,
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/// Shuffle 16 8-bit values within a vector.
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PSHUFB,
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/// Compute Sum of Absolute Differences.
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PSADBW,
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/// Compute Double Block Packed Sum-Absolute-Differences
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DBPSADBW,
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/// Bitwise Logical AND NOT of Packed FP values.
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ANDNP,
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/// Blend where the selector is an immediate.
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BLENDI,
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/// Dynamic (non-constant condition) vector blend where only the sign bits
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/// of the condition elements are used. This is used to enforce that the
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/// condition mask is not valid for generic VSELECT optimizations.
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SHRUNKBLEND,
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/// Combined add and sub on an FP vector.
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ADDSUB,
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// FP vector ops with rounding mode.
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FADD_RND, FADDS_RND,
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FSUB_RND, FSUBS_RND,
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FMUL_RND, FMULS_RND,
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FDIV_RND, FDIVS_RND,
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FMAX_RND, FMAXS_RND,
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FMIN_RND, FMINS_RND,
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FSQRT_RND, FSQRTS_RND,
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// FP vector get exponent.
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FGETEXP_RND, FGETEXPS_RND,
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// Extract Normalized Mantissas.
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VGETMANT, VGETMANTS,
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// FP Scale.
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SCALEF,
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SCALEFS,
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// Integer add/sub with unsigned saturation.
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ADDUS,
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SUBUS,
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// Integer add/sub with signed saturation.
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ADDS,
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SUBS,
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// Unsigned Integer average.
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AVG,
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/// Integer horizontal add/sub.
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HADD,
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HSUB,
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/// Floating point horizontal add/sub.
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FHADD,
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FHSUB,
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// Detect Conflicts Within a Vector
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CONFLICT,
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/// Floating point max and min.
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FMAX, FMIN,
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/// Commutative FMIN and FMAX.
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FMAXC, FMINC,
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/// Scalar intrinsic floating point max and min.
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FMAXS, FMINS,
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/// Floating point reciprocal-sqrt and reciprocal approximation.
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/// Note that these typically require refinement
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/// in order to obtain suitable precision.
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FRSQRT, FRCP,
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FRSQRTS, FRCPS,
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// Thread Local Storage.
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TLSADDR,
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// Thread Local Storage. A call to get the start address
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// of the TLS block for the current module.
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TLSBASEADDR,
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// Thread Local Storage. When calling to an OS provided
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// thunk at the address from an earlier relocation.
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TLSCALL,
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// Exception Handling helpers.
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EH_RETURN,
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// SjLj exception handling setjmp.
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EH_SJLJ_SETJMP,
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// SjLj exception handling longjmp.
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EH_SJLJ_LONGJMP,
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// SjLj exception handling dispatch.
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EH_SJLJ_SETUP_DISPATCH,
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/// Tail call return. See X86TargetLowering::LowerCall for
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/// the list of operands.
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TC_RETURN,
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// Vector move to low scalar and zero higher vector elements.
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VZEXT_MOVL,
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// Vector integer zero-extend.
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VZEXT,
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// Vector integer signed-extend.
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VSEXT,
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// Vector integer truncate.
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VTRUNC,
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// Vector integer truncate with unsigned/signed saturation.
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VTRUNCUS, VTRUNCS,
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// Vector FP extend.
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VFPEXT, VFPEXT_RND, VFPEXTS_RND,
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// Vector FP round.
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VFPROUND, VFPROUND_RND, VFPROUNDS_RND,
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// Convert a vector to mask, set bits base on MSB.
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CVT2MASK,
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// 128-bit vector logical left / right shift
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VSHLDQ, VSRLDQ,
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// Vector shift elements
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VSHL, VSRL, VSRA,
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// Vector variable shift right arithmetic.
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// Unlike ISD::SRA, in case shift count greater then element size
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// use sign bit to fill destination data element.
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VSRAV,
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// Vector shift elements by immediate
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VSHLI, VSRLI, VSRAI,
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// Shifts of mask registers.
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KSHIFTL, KSHIFTR,
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// Bit rotate by immediate
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VROTLI, VROTRI,
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// Vector packed double/float comparison.
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CMPP,
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// Vector integer comparisons.
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PCMPEQ, PCMPGT,
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// Vector integer comparisons, the result is in a mask vector.
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PCMPEQM, PCMPGTM,
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MULTISHIFT,
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/// Vector comparison generating mask bits for fp and
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/// integer signed and unsigned data types.
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CMPM,
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CMPMU,
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// Vector comparison with rounding mode for FP values
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CMPM_RND,
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// Arithmetic operations with FLAGS results.
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ADD, SUB, ADC, SBB, SMUL,
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INC, DEC, OR, XOR, AND,
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// Bit field extract.
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BEXTR,
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// LOW, HI, FLAGS = umul LHS, RHS.
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UMUL,
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// 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS.
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SMUL8, UMUL8,
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// 8-bit divrem that zero-extend the high result (AH).
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UDIVREM8_ZEXT_HREG,
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SDIVREM8_SEXT_HREG,
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// X86-specific multiply by immediate.
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MUL_IMM,
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// Vector sign bit extraction.
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MOVMSK,
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// Vector bitwise comparisons.
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PTEST,
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// Vector packed fp sign bitwise comparisons.
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TESTP,
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// Vector "test" in AVX-512, the result is in a mask vector.
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TESTM,
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TESTNM,
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// OR/AND test for masks.
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KORTEST,
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KTEST,
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// Several flavors of instructions with vector shuffle behaviors.
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// Saturated signed/unnsigned packing.
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PACKSS,
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PACKUS,
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// Intra-lane alignr.
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PALIGNR,
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// AVX512 inter-lane alignr.
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VALIGN,
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PSHUFD,
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PSHUFHW,
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PSHUFLW,
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SHUFP,
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//Shuffle Packed Values at 128-bit granularity.
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SHUF128,
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MOVDDUP,
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MOVSHDUP,
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MOVSLDUP,
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MOVLHPS,
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MOVLHPD,
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MOVHLPS,
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MOVLPS,
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MOVLPD,
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MOVSD,
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MOVSS,
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UNPCKL,
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UNPCKH,
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VPERMILPV,
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VPERMILPI,
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VPERMI,
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VPERM2X128,
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// Variable Permute (VPERM).
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// Res = VPERMV MaskV, V0
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VPERMV,
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// 3-op Variable Permute (VPERMT2).
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// Res = VPERMV3 V0, MaskV, V1
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VPERMV3,
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// 3-op Variable Permute overwriting the index (VPERMI2).
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// Res = VPERMIV3 V0, MaskV, V1
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VPERMIV3,
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// Bitwise ternary logic.
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VPTERNLOG,
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// Fix Up Special Packed Float32/64 values.
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VFIXUPIMM,
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VFIXUPIMMS,
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// Range Restriction Calculation For Packed Pairs of Float32/64 values.
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VRANGE,
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// Reduce - Perform Reduction Transformation on scalar\packed FP.
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VREDUCE, VREDUCES,
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// RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
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VRNDSCALE, VRNDSCALES,
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// Tests Types Of a FP Values for packed types.
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VFPCLASS,
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// Tests Types Of a FP Values for scalar types.
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VFPCLASSS,
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// Broadcast scalar to vector.
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VBROADCAST,
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// Broadcast mask to vector.
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VBROADCASTM,
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// Broadcast subvector to vector.
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SUBV_BROADCAST,
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// Extract vector element.
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VEXTRACT,
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/// SSE4A Extraction and Insertion.
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EXTRQI, INSERTQI,
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// XOP variable/immediate rotations.
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VPROT, VPROTI,
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// XOP arithmetic/logical shifts.
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VPSHA, VPSHL,
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// XOP signed/unsigned integer comparisons.
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VPCOM, VPCOMU,
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// XOP packed permute bytes.
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VPPERM,
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// XOP two source permutation.
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VPERMIL2,
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// Vector multiply packed unsigned doubleword integers.
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PMULUDQ,
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// Vector multiply packed signed doubleword integers.
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PMULDQ,
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// Vector Multiply Packed UnsignedIntegers with Round and Scale.
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MULHRS,
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// Multiply and Add Packed Integers.
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VPMADDUBSW, VPMADDWD,
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VPMADD52L, VPMADD52H,
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// FMA nodes.
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FMADD,
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FNMADD,
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FMSUB,
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FNMSUB,
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FMADDSUB,
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FMSUBADD,
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// FMA with rounding mode.
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FMADD_RND,
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FNMADD_RND,
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FMSUB_RND,
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FNMSUB_RND,
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FMADDSUB_RND,
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FMSUBADD_RND,
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// Scalar intrinsic FMA with rounding mode.
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// Two versions, passthru bits on op1 or op3.
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FMADDS1_RND, FMADDS3_RND,
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FNMADDS1_RND, FNMADDS3_RND,
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FMSUBS1_RND, FMSUBS3_RND,
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FNMSUBS1_RND, FNMSUBS3_RND,
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// Compress and expand.
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COMPRESS,
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EXPAND,
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// Convert Unsigned/Integer to Floating-Point Value with rounding mode.
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SINT_TO_FP_RND, UINT_TO_FP_RND,
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SCALAR_SINT_TO_FP_RND, SCALAR_UINT_TO_FP_RND,
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// Vector float/double to signed/unsigned integer.
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CVTP2SI, CVTP2UI, CVTP2SI_RND, CVTP2UI_RND,
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// Scalar float/double to signed/unsigned integer.
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CVTS2SI_RND, CVTS2UI_RND,
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// Vector float/double to signed/unsigned integer with truncation.
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CVTTP2SI, CVTTP2UI, CVTTP2SI_RND, CVTTP2UI_RND,
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// Scalar float/double to signed/unsigned integer with truncation.
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CVTTS2SI_RND, CVTTS2UI_RND,
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// Vector signed/unsigned integer to float/double.
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CVTSI2P, CVTUI2P,
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// Save xmm argument registers to the stack, according to %al. An operator
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// is needed so that this can be expanded with control flow.
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VASTART_SAVE_XMM_REGS,
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// Windows's _chkstk call to do stack probing.
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WIN_ALLOCA,
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// For allocating variable amounts of stack space when using
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// segmented stacks. Check if the current stacklet has enough space, and
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// falls back to heap allocation if not.
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SEG_ALLOCA,
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// Memory barriers.
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MEMBARRIER,
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MFENCE,
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// Store FP status word into i16 register.
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FNSTSW16r,
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// Store contents of %ah into %eflags.
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SAHF,
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// Get a random integer and indicate whether it is valid in CF.
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RDRAND,
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// Get a NIST SP800-90B & C compliant random integer and
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// indicate whether it is valid in CF.
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RDSEED,
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// SSE42 string comparisons.
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PCMPISTRI,
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PCMPESTRI,
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// Test if in transactional execution.
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XTEST,
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// ERI instructions.
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RSQRT28, RSQRT28S, RCP28, RCP28S, EXP2,
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// Conversions between float and half-float.
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|
CVTPS2PH, CVTPH2PS,
|
|
|
|
// Compare and swap.
|
|
LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
|
|
LCMPXCHG8_DAG,
|
|
LCMPXCHG16_DAG,
|
|
LCMPXCHG8_SAVE_EBX_DAG,
|
|
LCMPXCHG16_SAVE_RBX_DAG,
|
|
|
|
/// LOCK-prefixed arithmetic read-modify-write instructions.
|
|
/// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS)
|
|
LADD, LSUB, LOR, LXOR, LAND,
|
|
|
|
// Load, scalar_to_vector, and zero extend.
|
|
VZEXT_LOAD,
|
|
|
|
// Store FP control world into i16 memory.
|
|
FNSTCW16m,
|
|
|
|
/// This instruction implements FP_TO_SINT with the
|
|
/// integer destination in memory and a FP reg source. This corresponds
|
|
/// to the X86::FIST*m instructions and the rounding mode change stuff. It
|
|
/// has two inputs (token chain and address) and two outputs (int value
|
|
/// and token chain).
|
|
FP_TO_INT16_IN_MEM,
|
|
FP_TO_INT32_IN_MEM,
|
|
FP_TO_INT64_IN_MEM,
|
|
|
|
/// This instruction implements SINT_TO_FP with the
|
|
/// integer source in memory and FP reg result. This corresponds to the
|
|
/// X86::FILD*m instructions. It has three inputs (token chain, address,
|
|
/// and source type) and two outputs (FP value and token chain). FILD_FLAG
|
|
/// also produces a flag).
|
|
FILD,
|
|
FILD_FLAG,
|
|
|
|
/// This instruction implements an extending load to FP stack slots.
|
|
/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
|
|
/// operand, ptr to load from, and a ValueType node indicating the type
|
|
/// to load to.
|
|
FLD,
|
|
|
|
/// This instruction implements a truncating store to FP stack
|
|
/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
|
|
/// chain operand, value to store, address, and a ValueType to store it
|
|
/// as.
|
|
FST,
|
|
|
|
/// This instruction grabs the address of the next argument
|
|
/// from a va_list. (reads and modifies the va_list in memory)
|
|
VAARG_64,
|
|
|
|
// Vector truncating store with unsigned/signed saturation
|
|
VTRUNCSTOREUS, VTRUNCSTORES,
|
|
// Vector truncating masked store with unsigned/signed saturation
|
|
VMTRUNCSTOREUS, VMTRUNCSTORES
|
|
|
|
// WARNING: Do not add anything in the end unless you want the node to
|
|
// have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
|
|
// opcodes will be thought as target memory ops!
|
|
};
|
|
} // end namespace X86ISD
|
|
|
|
/// Define some predicates that are used for node matching.
|
|
namespace X86 {
|
|
/// Return true if the specified
|
|
/// EXTRACT_SUBVECTOR operand specifies a vector extract that is
|
|
/// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
|
|
bool isVEXTRACT128Index(SDNode *N);
|
|
|
|
/// Return true if the specified
|
|
/// INSERT_SUBVECTOR operand specifies a subvector insert that is
|
|
/// suitable for input to VINSERTF128, VINSERTI128 instructions.
|
|
bool isVINSERT128Index(SDNode *N);
|
|
|
|
/// Return true if the specified
|
|
/// EXTRACT_SUBVECTOR operand specifies a vector extract that is
|
|
/// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
|
|
bool isVEXTRACT256Index(SDNode *N);
|
|
|
|
/// Return true if the specified
|
|
/// INSERT_SUBVECTOR operand specifies a subvector insert that is
|
|
/// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
|
|
bool isVINSERT256Index(SDNode *N);
|
|
|
|
/// Return the appropriate
|
|
/// immediate to extract the specified EXTRACT_SUBVECTOR index
|
|
/// with VEXTRACTF128, VEXTRACTI128 instructions.
|
|
unsigned getExtractVEXTRACT128Immediate(SDNode *N);
|
|
|
|
/// Return the appropriate
|
|
/// immediate to insert at the specified INSERT_SUBVECTOR index
|
|
/// with VINSERTF128, VINSERT128 instructions.
|
|
unsigned getInsertVINSERT128Immediate(SDNode *N);
|
|
|
|
/// Return the appropriate
|
|
/// immediate to extract the specified EXTRACT_SUBVECTOR index
|
|
/// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
|
|
unsigned getExtractVEXTRACT256Immediate(SDNode *N);
|
|
|
|
/// Return the appropriate
|
|
/// immediate to insert at the specified INSERT_SUBVECTOR index
|
|
/// with VINSERTF64x4, VINSERTI64x4 instructions.
|
|
unsigned getInsertVINSERT256Immediate(SDNode *N);
|
|
|
|
/// Returns true if Elt is a constant zero or floating point constant +0.0.
|
|
bool isZeroNode(SDValue Elt);
|
|
|
|
/// Returns true of the given offset can be
|
|
/// fit into displacement field of the instruction.
|
|
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
|
|
bool hasSymbolicDisplacement = true);
|
|
|
|
/// Determines whether the callee is required to pop its
|
|
/// own arguments. Callee pop is necessary to support tail calls.
|
|
bool isCalleePop(CallingConv::ID CallingConv,
|
|
bool is64Bit, bool IsVarArg, bool GuaranteeTCO);
|
|
|
|
} // end namespace X86
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// X86 Implementation of the TargetLowering interface
|
|
class X86TargetLowering final : public TargetLowering {
|
|
public:
|
|
explicit X86TargetLowering(const X86TargetMachine &TM,
|
|
const X86Subtarget &STI);
|
|
|
|
unsigned getJumpTableEncoding() const override;
|
|
bool useSoftFloat() const override;
|
|
|
|
void markLibCallAttributes(MachineFunction *MF, unsigned CC,
|
|
ArgListTy &Args) const override;
|
|
|
|
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
|
|
return MVT::i8;
|
|
}
|
|
|
|
const MCExpr *
|
|
LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
|
|
const MachineBasicBlock *MBB, unsigned uid,
|
|
MCContext &Ctx) const override;
|
|
|
|
/// Returns relocation base for the given PIC jumptable.
|
|
SDValue getPICJumpTableRelocBase(SDValue Table,
|
|
SelectionDAG &DAG) const override;
|
|
const MCExpr *
|
|
getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
|
|
unsigned JTI, MCContext &Ctx) const override;
|
|
|
|
/// Return the desired alignment for ByVal aggregate
|
|
/// function arguments in the caller parameter area. For X86, aggregates
|
|
/// that contains are placed at 16-byte boundaries while the rest are at
|
|
/// 4-byte boundaries.
|
|
unsigned getByValTypeAlignment(Type *Ty,
|
|
const DataLayout &DL) const override;
|
|
|
|
/// Returns the target specific optimal type for load
|
|
/// and store operations as a result of memset, memcpy, and memmove
|
|
/// lowering. If DstAlign is zero that means it's safe to destination
|
|
/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
|
|
/// means there isn't a need to check it against alignment requirement,
|
|
/// probably because the source does not need to be loaded. If 'IsMemset' is
|
|
/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
|
|
/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
|
|
/// source is constant so it does not need to be loaded.
|
|
/// It returns EVT::Other if the type should be determined using generic
|
|
/// target-independent logic.
|
|
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
|
|
bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
|
|
MachineFunction &MF) const override;
|
|
|
|
/// Returns true if it's safe to use load / store of the
|
|
/// specified type to expand memcpy / memset inline. This is mostly true
|
|
/// for all types except for some special cases. For example, on X86
|
|
/// targets without SSE2 f64 load / store are done with fldl / fstpl which
|
|
/// also does type conversion. Note the specified type doesn't have to be
|
|
/// legal as the hook is used before type legalization.
|
|
bool isSafeMemOpType(MVT VT) const override;
|
|
|
|
/// Returns true if the target allows unaligned memory accesses of the
|
|
/// specified type. Returns whether it is "fast" in the last argument.
|
|
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
|
|
bool *Fast) const override;
|
|
|
|
/// Provide custom lowering hooks for some operations.
|
|
///
|
|
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
|
|
|
|
/// Places new result values for the node in Results (their number
|
|
/// and types must exactly match those of the original return values of
|
|
/// the node), or leaves Results empty, which indicates that the node is not
|
|
/// to be custom lowered after all.
|
|
void LowerOperationWrapper(SDNode *N,
|
|
SmallVectorImpl<SDValue> &Results,
|
|
SelectionDAG &DAG) const override;
|
|
|
|
/// Replace the results of node with an illegal result
|
|
/// type with new values built out of custom code.
|
|
///
|
|
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
|
|
SelectionDAG &DAG) const override;
|
|
|
|
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
|
|
|
|
/// Return true if the target has native support for
|
|
/// the specified value type and it is 'desirable' to use the type for the
|
|
/// given node type. e.g. On x86 i16 is legal, but undesirable since i16
|
|
/// instruction encodings are longer and some i16 instructions are slow.
|
|
bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
|
|
|
|
/// Return true if the target has native support for the
|
|
/// specified value type and it is 'desirable' to use the type. e.g. On x86
|
|
/// i16 is legal, but undesirable since i16 instruction encodings are longer
|
|
/// and some i16 instructions are slow.
|
|
bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
|
|
|
|
/// Return true if the MachineFunction contains a COPY which would imply
|
|
/// HasOpaqueSPAdjustment.
|
|
bool hasCopyImplyingStackAdjustment(MachineFunction *MF) const override;
|
|
|
|
MachineBasicBlock *
|
|
EmitInstrWithCustomInserter(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const override;
|
|
|
|
/// This method returns the name of a target specific DAG node.
|
|
const char *getTargetNodeName(unsigned Opcode) const override;
|
|
|
|
bool isCheapToSpeculateCttz() const override;
|
|
|
|
bool isCheapToSpeculateCtlz() const override;
|
|
|
|
bool isCtlzFast() const override;
|
|
|
|
bool hasBitPreservingFPLogic(EVT VT) const override {
|
|
return VT == MVT::f32 || VT == MVT::f64 || VT.isVector();
|
|
}
|
|
|
|
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
|
|
// If the pair to store is a mixture of float and int values, we will
|
|
// save two bitwise instructions and one float-to-int instruction and
|
|
// increase one store instruction. There is potentially a more
|
|
// significant benefit because it avoids the float->int domain switch
|
|
// for input value. So It is more likely a win.
|
|
if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
|
|
(LTy.isInteger() && HTy.isFloatingPoint()))
|
|
return true;
|
|
// If the pair only contains int values, we will save two bitwise
|
|
// instructions and increase one store instruction (costing one more
|
|
// store buffer). Since the benefit is more blurred so we leave
|
|
// such pair out until we get testcase to prove it is a win.
|
|
return false;
|
|
}
|
|
|
|
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
|
|
|
|
bool hasAndNotCompare(SDValue Y) const override;
|
|
|
|
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
|
|
return VT.isScalarInteger();
|
|
}
|
|
|
|
/// Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
|
|
MVT hasFastEqualityCompare(unsigned NumBits) const override;
|
|
|
|
/// Return the value type to use for ISD::SETCC.
|
|
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
|
|
EVT VT) const override;
|
|
|
|
/// Determine which of the bits specified in Mask are known to be either
|
|
/// zero or one and return them in the KnownZero/KnownOne bitsets.
|
|
void computeKnownBitsForTargetNode(const SDValue Op,
|
|
APInt &KnownZero,
|
|
APInt &KnownOne,
|
|
const APInt &DemandedElts,
|
|
const SelectionDAG &DAG,
|
|
unsigned Depth = 0) const override;
|
|
|
|
/// Determine the number of bits in the operation that are sign bits.
|
|
unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
|
|
const APInt &DemandedElts,
|
|
const SelectionDAG &DAG,
|
|
unsigned Depth) const override;
|
|
|
|
bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
|
|
int64_t &Offset) const override;
|
|
|
|
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
|
|
|
|
bool ExpandInlineAsm(CallInst *CI) const override;
|
|
|
|
ConstraintType getConstraintType(StringRef Constraint) const override;
|
|
|
|
/// Examine constraint string and operand type and determine a weight value.
|
|
/// The operand object must already have been set up with the operand type.
|
|
ConstraintWeight
|
|
getSingleConstraintMatchWeight(AsmOperandInfo &info,
|
|
const char *constraint) const override;
|
|
|
|
const char *LowerXConstraint(EVT ConstraintVT) const override;
|
|
|
|
/// Lower the specified operand into the Ops vector. If it is invalid, don't
|
|
/// add anything to Ops. If hasMemory is true it means one of the asm
|
|
/// constraint of the inline asm instruction being processed is 'm'.
|
|
void LowerAsmOperandForConstraint(SDValue Op,
|
|
std::string &Constraint,
|
|
std::vector<SDValue> &Ops,
|
|
SelectionDAG &DAG) const override;
|
|
|
|
unsigned
|
|
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
|
|
if (ConstraintCode == "i")
|
|
return InlineAsm::Constraint_i;
|
|
else if (ConstraintCode == "o")
|
|
return InlineAsm::Constraint_o;
|
|
else if (ConstraintCode == "v")
|
|
return InlineAsm::Constraint_v;
|
|
else if (ConstraintCode == "X")
|
|
return InlineAsm::Constraint_X;
|
|
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
|
|
}
|
|
|
|
/// Given a physical register constraint
|
|
/// (e.g. {edx}), return the register number and the register class for the
|
|
/// register. This should only be used for C_Register constraints. On
|
|
/// error, this returns a register number of 0.
|
|
std::pair<unsigned, const TargetRegisterClass *>
|
|
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
|
StringRef Constraint, MVT VT) const override;
|
|
|
|
/// Return true if the addressing mode represented
|
|
/// by AM is legal for this target, for a load/store of the specified type.
|
|
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
|
|
Type *Ty, unsigned AS) const override;
|
|
|
|
/// Return true if the specified immediate is legal
|
|
/// icmp immediate, that is the target has icmp instructions which can
|
|
/// compare a register against the immediate without having to materialize
|
|
/// the immediate into a register.
|
|
bool isLegalICmpImmediate(int64_t Imm) const override;
|
|
|
|
/// Return true if the specified immediate is legal
|
|
/// add immediate, that is the target has add instructions which can
|
|
/// add a register and the immediate without having to materialize
|
|
/// the immediate into a register.
|
|
bool isLegalAddImmediate(int64_t Imm) const override;
|
|
|
|
/// \brief Return the cost of the scaling factor used in the addressing
|
|
/// mode represented by AM for this target, for a load/store
|
|
/// of the specified type.
|
|
/// If the AM is supported, the return value must be >= 0.
|
|
/// If the AM is not supported, it returns a negative value.
|
|
int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
|
|
unsigned AS) const override;
|
|
|
|
bool isVectorShiftByScalarCheap(Type *Ty) const override;
|
|
|
|
/// Return true if it's free to truncate a value of
|
|
/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
|
|
/// register EAX to i16 by referencing its sub-register AX.
|
|
bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
|
|
bool isTruncateFree(EVT VT1, EVT VT2) const override;
|
|
|
|
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
|
|
|
|
/// Return true if any actual instruction that defines a
|
|
/// value of type Ty1 implicit zero-extends the value to Ty2 in the result
|
|
/// register. This does not necessarily include registers defined in
|
|
/// unknown ways, such as incoming arguments, or copies from unknown
|
|
/// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
|
|
/// does not necessarily apply to truncate instructions. e.g. on x86-64,
|
|
/// all instructions that define 32-bit values implicit zero-extend the
|
|
/// result out to 64 bits.
|
|
bool isZExtFree(Type *Ty1, Type *Ty2) const override;
|
|
bool isZExtFree(EVT VT1, EVT VT2) const override;
|
|
bool isZExtFree(SDValue Val, EVT VT2) const override;
|
|
|
|
/// Return true if folding a vector load into ExtVal (a sign, zero, or any
|
|
/// extend node) is profitable.
|
|
bool isVectorLoadExtDesirable(SDValue) const override;
|
|
|
|
/// Return true if an FMA operation is faster than a pair of fmul and fadd
|
|
/// instructions. fmuladd intrinsics will be expanded to FMAs when this
|
|
/// method returns true, otherwise fmuladd is expanded to fmul + fadd.
|
|
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
|
|
|
|
/// Return true if it's profitable to narrow
|
|
/// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
|
|
/// from i32 to i8 but not from i32 to i16.
|
|
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
|
|
|
|
/// Given an intrinsic, checks if on the target the intrinsic will need to map
|
|
/// to a MemIntrinsicNode (touches memory). If this is the case, it returns
|
|
/// true and stores the intrinsic information into the IntrinsicInfo that was
|
|
/// passed to the function.
|
|
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
|
|
unsigned Intrinsic) const override;
|
|
|
|
/// Returns true if the target can instruction select the
|
|
/// specified FP immediate natively. If false, the legalizer will
|
|
/// materialize the FP immediate as a load from a constant pool.
|
|
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
|
|
|
|
/// Targets can use this to indicate that they only support *some*
|
|
/// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
|
|
/// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
|
|
/// be legal.
|
|
bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
|
|
EVT VT) const override;
|
|
|
|
/// Similar to isShuffleMaskLegal. This is used by Targets can use this to
|
|
/// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
|
|
/// replace a VAND with a constant pool entry.
|
|
bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
|
|
EVT VT) const override;
|
|
|
|
/// If true, then instruction selection should
|
|
/// seek to shrink the FP constant of the specified type to a smaller type
|
|
/// in order to save space and / or reduce runtime.
|
|
bool ShouldShrinkFPConstant(EVT VT) const override {
|
|
// Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
|
|
// expensive than a straight movsd. On the other hand, it's important to
|
|
// shrink long double fp constant since fldt is very slow.
|
|
return !X86ScalarSSEf64 || VT == MVT::f80;
|
|
}
|
|
|
|
/// Return true if we believe it is correct and profitable to reduce the
|
|
/// load node to a smaller type.
|
|
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
|
|
EVT NewVT) const override;
|
|
|
|
/// Return true if the specified scalar FP type is computed in an SSE
|
|
/// register, not on the X87 floating point stack.
|
|
bool isScalarFPTypeInSSEReg(EVT VT) const {
|
|
return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
|
|
(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
|
|
}
|
|
|
|
/// \brief Returns true if it is beneficial to convert a load of a constant
|
|
/// to just the constant itself.
|
|
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
|
|
Type *Ty) const override;
|
|
|
|
bool convertSelectOfConstantsToMath() const override {
|
|
return true;
|
|
}
|
|
|
|
/// Return true if EXTRACT_SUBVECTOR is cheap for this result type
|
|
/// with this index.
|
|
bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
|
|
|
|
/// Intel processors have a unified instruction and data cache
|
|
const char * getClearCacheBuiltinName() const override {
|
|
return nullptr; // nothing to do, move along.
|
|
}
|
|
|
|
unsigned getRegisterByName(const char* RegName, EVT VT,
|
|
SelectionDAG &DAG) const override;
|
|
|
|
/// If a physical register, this returns the register that receives the
|
|
/// exception address on entry to an EH pad.
|
|
unsigned
|
|
getExceptionPointerRegister(const Constant *PersonalityFn) const override;
|
|
|
|
/// If a physical register, this returns the register that receives the
|
|
/// exception typeid on entry to a landing pad.
|
|
unsigned
|
|
getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
|
|
|
|
virtual bool needsFixedCatchObjects() const override;
|
|
|
|
/// This method returns a target specific FastISel object,
|
|
/// or null if the target does not support "fast" ISel.
|
|
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo) const override;
|
|
|
|
/// If the target has a standard location for the stack protector cookie,
|
|
/// returns the address of that location. Otherwise, returns nullptr.
|
|
Value *getIRStackGuard(IRBuilder<> &IRB) const override;
|
|
|
|
bool useLoadStackGuardNode() const override;
|
|
void insertSSPDeclarations(Module &M) const override;
|
|
Value *getSDagStackGuard(const Module &M) const override;
|
|
Value *getSSPStackGuardCheck(const Module &M) const override;
|
|
|
|
/// Return true if the target stores SafeStack pointer at a fixed offset in
|
|
/// some non-standard address space, and populates the address space and
|
|
/// offset as appropriate.
|
|
Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
|
|
|
|
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
|
|
SelectionDAG &DAG) const;
|
|
|
|
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
|
|
|
|
/// \brief Customize the preferred legalization strategy for certain types.
|
|
LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
|
|
|
|
bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
|
|
|
|
bool supportSwiftError() const override;
|
|
|
|
unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
|
|
|
|
/// \brief Lower interleaved load(s) into target specific
|
|
/// instructions/intrinsics.
|
|
bool lowerInterleavedLoad(LoadInst *LI,
|
|
ArrayRef<ShuffleVectorInst *> Shuffles,
|
|
ArrayRef<unsigned> Indices,
|
|
unsigned Factor) const override;
|
|
protected:
|
|
std::pair<const TargetRegisterClass *, uint8_t>
|
|
findRepresentativeClass(const TargetRegisterInfo *TRI,
|
|
MVT VT) const override;
|
|
|
|
private:
|
|
/// Keep a reference to the X86Subtarget around so that we can
|
|
/// make the right decision when generating code for different targets.
|
|
const X86Subtarget &Subtarget;
|
|
|
|
/// Select between SSE or x87 floating point ops.
|
|
/// When SSE is available, use it for f32 operations.
|
|
/// When SSE2 is available, use it for f64 operations.
|
|
bool X86ScalarSSEf32;
|
|
bool X86ScalarSSEf64;
|
|
|
|
/// A list of legal FP immediates.
|
|
std::vector<APFloat> LegalFPImmediates;
|
|
|
|
/// Indicate that this x86 target can instruction
|
|
/// select the specified FP immediate natively.
|
|
void addLegalFPImmediate(const APFloat& Imm) {
|
|
LegalFPImmediates.push_back(Imm);
|
|
}
|
|
|
|
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
const SDLoc &dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals,
|
|
uint32_t *RegMask) const;
|
|
SDValue LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
|
|
const SmallVectorImpl<ISD::InputArg> &ArgInfo,
|
|
const SDLoc &dl, SelectionDAG &DAG,
|
|
const CCValAssign &VA, MachineFrameInfo &MFI,
|
|
unsigned i) const;
|
|
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
|
|
const SDLoc &dl, SelectionDAG &DAG,
|
|
const CCValAssign &VA,
|
|
ISD::ArgFlagsTy Flags) const;
|
|
|
|
// Call lowering helpers.
|
|
|
|
/// Check whether the call is eligible for tail call optimization. Targets
|
|
/// that want to do tail call optimization should implement this function.
|
|
bool IsEligibleForTailCallOptimization(SDValue Callee,
|
|
CallingConv::ID CalleeCC,
|
|
bool isVarArg,
|
|
bool isCalleeStructRet,
|
|
bool isCallerStructRet,
|
|
Type *RetTy,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SelectionDAG& DAG) const;
|
|
SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
|
|
SDValue Chain, bool IsTailCall,
|
|
bool Is64Bit, int FPDiff,
|
|
const SDLoc &dl) const;
|
|
|
|
unsigned GetAlignedArgumentStackSize(unsigned StackSize,
|
|
SelectionDAG &DAG) const;
|
|
|
|
unsigned getAddressSpace(void) const;
|
|
|
|
std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
|
|
bool isSigned,
|
|
bool isReplace) const;
|
|
|
|
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
unsigned getGlobalWrapperKind(const GlobalValue *GV = nullptr) const;
|
|
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddress(const GlobalValue *GV, const SDLoc &dl,
|
|
int64_t Offset, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerToBT(SDValue And, ISD::CondCode CC, const SDLoc &dl,
|
|
SelectionDAG &DAG) const;
|
|
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue
|
|
LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
const SDLoc &dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const override;
|
|
SDValue LowerCall(CallLoweringInfo &CLI,
|
|
SmallVectorImpl<SDValue> &InVals) const override;
|
|
|
|
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SDLoc &dl, SelectionDAG &DAG) const override;
|
|
|
|
bool supportSplitCSR(MachineFunction *MF) const override {
|
|
return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
|
|
MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
|
|
}
|
|
void initializeSplitCSR(MachineBasicBlock *Entry) const override;
|
|
void insertCopiesSplitCSR(
|
|
MachineBasicBlock *Entry,
|
|
const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
|
|
|
|
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
|
|
|
|
bool mayBeEmittedAsTailCall(CallInst *CI) const override;
|
|
|
|
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
|
|
ISD::NodeType ExtendKind) const override;
|
|
|
|
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
|
|
bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
LLVMContext &Context) const override;
|
|
|
|
const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
|
|
|
|
TargetLoweringBase::AtomicExpansionKind
|
|
shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
|
|
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
|
|
TargetLoweringBase::AtomicExpansionKind
|
|
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
|
|
|
|
LoadInst *
|
|
lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
|
|
|
|
bool needsCmpXchgNb(Type *MemType) const;
|
|
|
|
void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
|
|
MachineBasicBlock *DispatchBB, int FI) const;
|
|
|
|
// Utility function to emit the low-level va_arg code for X86-64.
|
|
MachineBasicBlock *
|
|
EmitVAARG64WithCustomInserter(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
/// Utility function to emit the xmm reg save portion of va_start.
|
|
MachineBasicBlock *
|
|
EmitVAStartSaveXMMRegsWithCustomInserter(MachineInstr &BInstr,
|
|
MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *EmitLoweredSelect(MachineInstr &I,
|
|
MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr &I,
|
|
MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI,
|
|
MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *EmitLoweredCatchPad(MachineInstr &MI,
|
|
MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI,
|
|
MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr &MI,
|
|
MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI,
|
|
MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
MachineBasicBlock *emitFMA3Instr(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
/// Emit nodes that will be selected as "test Op0,Op0", or something
|
|
/// equivalent, for use with the given x86 condition code.
|
|
SDValue EmitTest(SDValue Op0, unsigned X86CC, const SDLoc &dl,
|
|
SelectionDAG &DAG) const;
|
|
|
|
/// Emit nodes that will be selected as "cmp Op0,Op1", or something
|
|
/// equivalent, for use with the given x86 condition code.
|
|
SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, const SDLoc &dl,
|
|
SelectionDAG &DAG) const;
|
|
|
|
/// Convert a comparison if required by the subtarget.
|
|
SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
|
|
|
|
/// Check if replacement of SQRT with RSQRT should be disabled.
|
|
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override;
|
|
|
|
/// Use rsqrt* to speed up sqrt calculations.
|
|
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
|
|
int &RefinementSteps, bool &UseOneConstNR,
|
|
bool Reciprocal) const override;
|
|
|
|
/// Use rcp* to speed up fdiv calculations.
|
|
SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
|
|
int &RefinementSteps) const override;
|
|
|
|
/// Reassociate floating point divisions into multiply by reciprocal.
|
|
unsigned combineRepeatedFPDivisors() const override;
|
|
};
|
|
|
|
namespace X86 {
|
|
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo);
|
|
} // end namespace X86
|
|
|
|
// Base class for all X86 non-masked store operations.
|
|
class X86StoreSDNode : public MemSDNode {
|
|
public:
|
|
X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
|
|
SDVTList VTs, EVT MemVT,
|
|
MachineMemOperand *MMO)
|
|
:MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
|
|
const SDValue &getValue() const { return getOperand(1); }
|
|
const SDValue &getBasePtr() const { return getOperand(2); }
|
|
|
|
static bool classof(const SDNode *N) {
|
|
return N->getOpcode() == X86ISD::VTRUNCSTORES ||
|
|
N->getOpcode() == X86ISD::VTRUNCSTOREUS;
|
|
}
|
|
};
|
|
|
|
// Base class for all X86 masked store operations.
|
|
// The class has the same order of operands as MaskedStoreSDNode for
|
|
// convenience.
|
|
class X86MaskedStoreSDNode : public MemSDNode {
|
|
public:
|
|
X86MaskedStoreSDNode(unsigned Opcode, unsigned Order,
|
|
const DebugLoc &dl, SDVTList VTs, EVT MemVT,
|
|
MachineMemOperand *MMO)
|
|
: MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
|
|
|
|
const SDValue &getBasePtr() const { return getOperand(1); }
|
|
const SDValue &getMask() const { return getOperand(2); }
|
|
const SDValue &getValue() const { return getOperand(3); }
|
|
|
|
static bool classof(const SDNode *N) {
|
|
return N->getOpcode() == X86ISD::VMTRUNCSTORES ||
|
|
N->getOpcode() == X86ISD::VMTRUNCSTOREUS;
|
|
}
|
|
};
|
|
|
|
// X86 Truncating Store with Signed saturation.
|
|
class TruncSStoreSDNode : public X86StoreSDNode {
|
|
public:
|
|
TruncSStoreSDNode(unsigned Order, const DebugLoc &dl,
|
|
SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
|
|
: X86StoreSDNode(X86ISD::VTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {}
|
|
|
|
static bool classof(const SDNode *N) {
|
|
return N->getOpcode() == X86ISD::VTRUNCSTORES;
|
|
}
|
|
};
|
|
|
|
// X86 Truncating Store with Unsigned saturation.
|
|
class TruncUSStoreSDNode : public X86StoreSDNode {
|
|
public:
|
|
TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl,
|
|
SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
|
|
: X86StoreSDNode(X86ISD::VTRUNCSTOREUS, Order, dl, VTs, MemVT, MMO) {}
|
|
|
|
static bool classof(const SDNode *N) {
|
|
return N->getOpcode() == X86ISD::VTRUNCSTOREUS;
|
|
}
|
|
};
|
|
|
|
// X86 Truncating Masked Store with Signed saturation.
|
|
class MaskedTruncSStoreSDNode : public X86MaskedStoreSDNode {
|
|
public:
|
|
MaskedTruncSStoreSDNode(unsigned Order,
|
|
const DebugLoc &dl, SDVTList VTs, EVT MemVT,
|
|
MachineMemOperand *MMO)
|
|
: X86MaskedStoreSDNode(X86ISD::VMTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {}
|
|
|
|
static bool classof(const SDNode *N) {
|
|
return N->getOpcode() == X86ISD::VMTRUNCSTORES;
|
|
}
|
|
};
|
|
|
|
// X86 Truncating Masked Store with Unsigned saturation.
|
|
class MaskedTruncUSStoreSDNode : public X86MaskedStoreSDNode {
|
|
public:
|
|
MaskedTruncUSStoreSDNode(unsigned Order,
|
|
const DebugLoc &dl, SDVTList VTs, EVT MemVT,
|
|
MachineMemOperand *MMO)
|
|
: X86MaskedStoreSDNode(X86ISD::VMTRUNCSTOREUS, Order, dl, VTs, MemVT, MMO) {}
|
|
|
|
static bool classof(const SDNode *N) {
|
|
return N->getOpcode() == X86ISD::VMTRUNCSTOREUS;
|
|
}
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
|