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llvm-project/llvm/test/CodeGen
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Scott Linder c6c627253d [AMDGPU] Remove FeatureVGPRSpilling 
This feature is only relevant to shaders, and is no longer used. When disabled,
lowering of reserved registers for shaders causes a compiler crash.

Remove the feature and add a test for compilation of shaders at OptNone.

Differential Revision: https://reviews.llvm.org/D53829

llvm-svn: 345763
 		2018-10-31 18:54:06 +00:00
..
AArch64 [globalisel][irtranslator] Fix test from r345743 on non-asserts builds. 2018-10-31 17:58:47 +00:00
AMDGPU [AMDGPU] Remove FeatureVGPRSpilling 2018-10-31 18:54:06 +00:00
ARC
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ARM MachineOperand/MIParser: Do not print debug-use flag, infer it 2018-10-30 23:28:27 +00:00
AVR [AVR] Fix the 'call.ll' CodeGen test 2018-10-10 03:21:42 +00:00
BPF [bpf] Test case for symbol information in object file 2018-09-22 17:31:01 +00:00
Generic [MIR] Simplify and move MIR test 2018-10-26 16:00:29 +00:00
Hexagon [Hexagon] Make sure not to use GP-relative addressing with PIC 2018-10-31 15:54:31 +00:00
Inputs
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Lanai
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MIR MachineOperand/MIParser: Do not print debug-use flag, infer it 2018-10-30 23:28:27 +00:00
MSP430 [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks) 2018-08-29 11:18:14 +00:00
Mips [DAGCombiner] Improve X div/rem Y fold if single bit element type 2018-10-30 09:07:22 +00:00
NVPTX
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Nios2
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PowerPC MachineOperand/MIParser: Do not print debug-use flag, infer it 2018-10-30 23:28:27 +00:00
RISCV [RISCV] Eliminate unnecessary masking of promoted shift amounts 2018-10-12 23:18:52 +00:00
SPARC Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00
SystemZ [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
Thumb [ARM] Make InstrEmitter mark CPSR defs dead for Thumb1. 2018-10-26 19:32:24 +00:00
Thumb2 [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
WebAssembly [WebAssembly] Lower away condition truncations for scalar selects 2018-10-29 18:38:12 +00:00
WinCFGuard [COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables 2018-09-19 09:58:30 +00:00
WinEH
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X86 [DAGCombiner] Fold 0 div/rem X to 0 2018-10-31 14:18:57 +00:00
XCore Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00