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llvm-project/llvm/lib/Target/VE
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Kazushi (Jam) Marukawa 95ea50e4ad [VE] Correct LVLGen (LVL instruction insert pass) 
SX Aurora VE uses an intermediate representation similar to VP as its MIR.
VE itself uses invidiual VL register as its own vector length register at
the hardware level.  So, LLVM needs to insert load VL (LVL) instruction just
before vector instructions if the value of VL is changed.  This LVLGen pass
generates LVL instructions for such purpose.  Previously, a bug is pointed
out in D91416.  This patch correct this bug and add a regression test.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D92716
 		2020-12-09 06:33:53 +09:00
..
AsmParser llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
Disassembler llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
MCTargetDesc [VE] Correct getMnemonic 2020-11-17 22:33:29 +09:00
TargetInfo llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
CMakeLists.txt [VE] LVLGen sets VL before vector insts 2020-11-16 09:19:14 +01:00
LVLGen.cpp [VE] Correct LVLGen (LVL instruction insert pass) 2020-12-09 06:33:53 +09:00
VE.h [VE] LVLGen sets VL before vector insts 2020-11-16 09:19:14 +01:00
VE.td [VE] Add +vpu attribute 2020-11-04 12:42:00 +01:00
VEAsmPrinter.cpp [VE] Support inline assembly with vector regsiters 2020-11-10 20:55:38 +09:00
VECallingConv.td [VE] VEC_BROADCAST, lowering and isel 2020-11-19 09:44:56 +01:00
VEFrameLowering.cpp [VE][NFC] Update comments 2020-12-01 02:56:16 +09:00
VEFrameLowering.h [VE] Optimize prologue/epilogue instructions 2020-11-30 22:22:33 +09:00
VEISelDAGToDAG.cpp [VE] Implement FoldImmediate 2020-11-11 08:08:32 +09:00
VEISelLowering.cpp [VE] Optimize prologue/epilogue instructions about GOT 2020-12-01 02:22:31 +09:00
VEISelLowering.h [VE] VE Vector Predicated SDNode, vector add isel and tests 2020-11-23 17:17:07 +01:00
VEInstrFormats.td [VE] Add VBRD/VMV instructions 2020-10-19 18:33:54 +09:00
VEInstrInfo.cpp [VE] Clean check routines of branch types 2020-12-01 02:19:37 +09:00
VEInstrInfo.h [VE] Implement FoldImmediate 2020-11-11 08:08:32 +09:00
VEInstrInfo.td [VE] Change the behaviour of truncate 2020-11-30 22:12:45 +09:00
VEInstrIntrinsicVL.gen.td [VE] Add vcp and vex intrinsic instructions 2020-12-07 22:56:55 +09:00
VEInstrIntrinsicVL.td [VE] Add lsv/lvs intrinsic instructions 2020-11-16 23:42:51 +09:00
VEInstrPatternsVec.td [VE] VE Vector Predicated SDNode, vector add isel and tests 2020-11-23 17:17:07 +01:00
VEInstrVec.td [VE] Add lvm/svm intrinsic instructions 2020-11-17 07:05:36 +09:00
VEMCInstLower.cpp [VE] Implement JumpTable 2020-11-17 22:43:10 +09:00
VEMachineFunctionInfo.cpp [VE] call isel with stack passing 2020-01-28 10:55:47 +01:00
VEMachineFunctionInfo.h [VE] Support for PIC (global data and calls) 2020-02-14 09:50:02 +01:00
VERegisterInfo.cpp [VE] Clean canRealignStack implementation 2020-11-23 21:09:03 +09:00
VERegisterInfo.h [VE] Clean canRealignStack implementation 2020-11-23 21:09:03 +09:00
VERegisterInfo.td [VE] VEC_BROADCAST, lowering and isel 2020-11-19 09:44:56 +01:00
VESubtarget.cpp [VE] Remove magic numbers 176 2020-11-24 00:13:24 +09:00
VESubtarget.h [VE] Remove magic numbers 176 2020-11-24 00:13:24 +09:00
VETargetMachine.cpp [VE] Specify vector alignments 2020-11-30 22:09:21 +09:00
VETargetMachine.h [VE] Target-specific bit size for sjljehprepare 2020-03-10 17:51:16 +01:00
VETargetTransformInfo.h [VE][TTI] don't advertise vregs/vops 2020-11-06 11:12:10 +01:00
VVPInstrInfo.td [VE] VE Vector Predicated SDNode, vector add isel and tests 2020-11-23 17:17:07 +01:00
VVPInstrPatternsVec.td [VE] VE Vector Predicated SDNode, vector add isel and tests 2020-11-23 17:17:07 +01:00
VVPNodes.def [VE] VE Vector Predicated SDNode, vector add isel and tests 2020-11-23 17:17:07 +01:00