llvm-project/llvm/test/CodeGen/Thumb2
Daniel Neilson 1e68724d24 Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
Summary:
 This is a resurrection of work first proposed and discussed in Aug 2015:
   http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
and initially landed (but then backed out) in Nov 2015:
   http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html

 The @llvm.memcpy/memmove/memset intrinsics currently have an explicit argument
which is required to be a constant integer. It represents the alignment of the
dest (and source), and so must be the minimum of the actual alignment of the
two.

 This change is the first in a series that allows source and dest to each
have their own alignments by using the alignment attribute on their arguments.

 In this change we:
1) Remove the alignment argument.
2) Add alignment attributes to the source & dest arguments. We, temporarily,
   require that the alignments for source & dest be equal.

 For example, code which used to read:
  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 100, i32 4, i1 false)
will now read
  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %dest, i8* align 4 %src, i32 100, i1 false)

 Downstream users may have to update their lit tests that check for
@llvm.memcpy/memmove/memset call/declaration patterns. The following extended sed script
may help with updating the majority of your tests, but it does not catch all possible
patterns so some manual checking and updating will be required.

s~declare void @llvm\.mem(set|cpy|move)\.p([^(]*)\((.*), i32, i1\)~declare void @llvm.mem\1.p\2(\3, i1)~g
s~call void @llvm\.memset\.p([^(]*)i8\(i8([^*]*)\* (.*), i8 (.*), i8 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i8(i8\2* \3, i8 \4, i8 \5, i1 \6)~g
s~call void @llvm\.memset\.p([^(]*)i16\(i8([^*]*)\* (.*), i8 (.*), i16 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i16(i8\2* \3, i8 \4, i16 \5, i1 \6)~g
s~call void @llvm\.memset\.p([^(]*)i32\(i8([^*]*)\* (.*), i8 (.*), i32 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i32(i8\2* \3, i8 \4, i32 \5, i1 \6)~g
s~call void @llvm\.memset\.p([^(]*)i64\(i8([^*]*)\* (.*), i8 (.*), i64 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i64(i8\2* \3, i8 \4, i64 \5, i1 \6)~g
s~call void @llvm\.memset\.p([^(]*)i128\(i8([^*]*)\* (.*), i8 (.*), i128 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i128(i8\2* \3, i8 \4, i128 \5, i1 \6)~g
s~call void @llvm\.memset\.p([^(]*)i8\(i8([^*]*)\* (.*), i8 (.*), i8 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i8(i8\2* align \6 \3, i8 \4, i8 \5, i1 \7)~g
s~call void @llvm\.memset\.p([^(]*)i16\(i8([^*]*)\* (.*), i8 (.*), i16 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i16(i8\2* align \6 \3, i8 \4, i16 \5, i1 \7)~g
s~call void @llvm\.memset\.p([^(]*)i32\(i8([^*]*)\* (.*), i8 (.*), i32 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i32(i8\2* align \6 \3, i8 \4, i32 \5, i1 \7)~g
s~call void @llvm\.memset\.p([^(]*)i64\(i8([^*]*)\* (.*), i8 (.*), i64 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i64(i8\2* align \6 \3, i8 \4, i64 \5, i1 \7)~g
s~call void @llvm\.memset\.p([^(]*)i128\(i8([^*]*)\* (.*), i8 (.*), i128 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i128(i8\2* align \6 \3, i8 \4, i128 \5, i1 \7)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i8\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i8 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i8(i8\3* \4, i8\5* \6, i8 \7, i1 \8)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i16\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i16 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i16(i8\3* \4, i8\5* \6, i16 \7, i1 \8)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i32\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i32 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i32(i8\3* \4, i8\5* \6, i32 \7, i1 \8)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i64\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i64 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i64(i8\3* \4, i8\5* \6, i64 \7, i1 \8)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i128\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i128 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i128(i8\3* \4, i8\5* \6, i128 \7, i1 \8)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i8\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i8 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i8(i8\3* align \8 \4, i8\5* align \8 \6, i8 \7, i1 \9)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i16\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i16 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i16(i8\3* align \8 \4, i8\5* align \8 \6, i16 \7, i1 \9)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i32\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i32 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i32(i8\3* align \8 \4, i8\5* align \8 \6, i32 \7, i1 \9)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i64\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i64 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i64(i8\3* align \8 \4, i8\5* align \8 \6, i64 \7, i1 \9)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i128\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i128 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i128(i8\3* align \8 \4, i8\5* align \8 \6, i128 \7, i1 \9)~g

 The remaining changes in the series will:
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
   source and dest alignments.
Step 3) Update Clang to use the new IRBuilder API.
Step 4) Update Polly to use the new IRBuilder API.
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
        and those that use use MemIntrinsicInst::[get|set]Alignment() to use
        getDestAlignment() and getSourceAlignment() instead.
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
        MemIntrinsicInst::[get|set]Alignment() methods.

Reviewers: pete, hfinkel, lhames, reames, bollu

Reviewed By: reames

Subscribers: niosHD, reames, jholewinski, qcolombet, jfb, sanjoy, arsenm, dschuff, dylanmckay, mehdi_amini, sdardis, nemanjai, david2050, nhaehnle, javed.absar, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, llvm-commits

Differential Revision: https://reviews.llvm.org/D41675

llvm-svn: 322965
2018-01-19 17:13:12 +00:00
..
2009-07-17-CrossRegClassCopy.ll
2009-07-21-ISelBug.ll [ARM] Generate consistent frame records for Thumb2 2016-08-23 09:19:22 +00:00
2009-07-23-CPIslandBug.ll
2009-07-30-PEICrash.ll
2009-08-01-WrongLDRBOpc.ll
2009-08-02-CoalescerBug.ll
2009-08-04-CoalescerAssert.ll
2009-08-04-CoalescerBug.ll
2009-08-04-ScavengerAssert.ll
2009-08-04-SubregLoweringBug.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
2009-08-04-SubregLoweringBug2.ll
2009-08-04-SubregLoweringBug3.ll
2009-08-06-SpDecBug.ll ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets. 2015-04-23 20:31:26 +00:00
2009-08-07-CoalescerBug.ll
2009-08-07-NeonFPBug.ll
2009-08-08-ScavengerAssert.ll
2009-08-10-ISelBug.ll
2009-08-21-PostRAKill4.ll
2009-09-01-PostRAProlog.ll Fix an old memset signature in 2009-09-01-PostRAProlog.ll test causing a buildbot failure 2016-06-23 16:07:10 +00:00
2009-10-15-ITBlockBranch.ll
2009-11-01-CopyReg2RegBug.ll
2009-11-11-ScavengerAssert.ll
2009-11-13-STRDBug.ll
2009-12-01-LoopIVUsers.ll [SCEV] Try to reuse existing value during SCEV expansion 2016-02-04 01:27:38 +00:00
2010-01-06-TailDuplicateLabels.ll
2010-01-19-RemovePredicates.ll
2010-02-11-phi-cycle.ll ARM: stop emitting blx instructions for most calls on MachO. 2016-05-10 19:17:47 +00:00
2010-02-24-BigStack.ll
2010-03-08-addi12-ccout.ll
2010-03-15-AsmCCClobber.ll ARM: stop emitting blx instructions for most calls on MachO. 2016-05-10 19:17:47 +00:00
2010-04-15-DynAllocBug.ll
2010-04-26-CopyRegCrash.ll
2010-05-24-rsbs.ll
2010-06-14-NEONCoalescer.ll [CodeGen] Don't print "pred:" and "opt:" in -debug output 2018-01-09 17:31:07 +00:00
2010-06-19-ITBlockCrash.ll
2010-06-21-TailMergeBug.ll
2010-08-10-VarSizedAllocaBug.ll
2010-11-22-EpilogueBug.ll [ARM] Call setBooleanContents(ZeroOrOneBooleanContent) 2017-08-22 11:02:37 +00:00
2010-12-03-AddSPNarrowing.ll
2011-04-21-FILoweringBug.ll
2011-06-07-TwoAddrEarlyClobber.ll Thumb2: When optimizing for size, do not if-convert branches involving comparisons with zero. 2015-04-23 20:31:30 +00:00
2011-12-16-T2SizeReduceAssert.ll
2012-01-13-CBNZBug.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
2013-02-19-tail-call-register-hint.ll
2013-03-02-vduplane-nonconstant-source-index.ll
2013-03-06-vector-sext-operand-scalarize.ll
aapcs.ll ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 2015-07-21 00:18:59 +00:00
aligned-constants.ll [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00
aligned-spill.ll [ARM] Generate consistent frame records for Thumb2 2016-08-23 09:19:22 +00:00
bfi.ll
bfx.ll
bicbfi.ll [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
buildvector-crash.ll
carry.ll Address buildbot fallout from r259065 2016-01-28 18:59:04 +00:00
cbnz.ll CodeGen: Allow small copyable blocks to "break" the CFG. 2017-01-31 23:48:32 +00:00
constant-islands-jump-table.ll ARM: recommit r237590: allow jump tables to be placed as constant islands. 2015-05-31 19:22:07 +00:00
constant-islands-new-island-padding.ll
constant-islands-new-island.ll [ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8). 2017-06-28 07:07:03 +00:00
constant-islands.ll ARM: Do not use llc -march in tests. 2017-08-01 22:20:49 +00:00
cortex-fp.ll ARM: Do not use llc -march in tests. 2017-08-01 22:20:49 +00:00
crash.ll [ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions 2015-09-30 10:56:37 +00:00
cross-rc-coalescing-1.ll
cross-rc-coalescing-2.ll
div.ll
emit-unwinding.ll ARM: use r7 as the frame-pointer on all MachO targets. 2016-04-11 22:27:40 +00:00
float-cmp.ll [ARM] Use VCMP, not VCMPE, for floating point equality comparisons 2017-02-13 12:32:47 +00:00
float-intrinsics-double.ll ARM: match GCC's behaviour for builtins 2017-01-13 16:25:33 +00:00
float-intrinsics-float.ll ARM: match GCC's behaviour for builtins 2017-01-13 16:25:33 +00:00
float-ops.ll [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently 2016-12-15 09:38:59 +00:00
frame-pointer.ll Re-land "[Thumb] Save/restore high registers in Thumb1 pro/epilogues" 2016-10-11 21:14:03 +00:00
frameless.ll
frameless2.ll
ifcvt-compare.ll CodeGen: Allow small copyable blocks to "break" the CFG. 2017-01-31 23:48:32 +00:00
ifcvt-neon-deprecated.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
ifcvt-no-branch-predictor.ll [ARM] Adjust ifcvt heuristic for the diamond ifcvt case 2017-07-12 13:23:10 +00:00
ifcvt-rescan-bug-2016-08-22.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
ifcvt-rescan-diamonds.ll IfConversion: Fix bug introduced by rescanning diamonds. 2016-09-02 18:29:26 +00:00
inflate-regs.ll
inlineasm.ll
intrinsics-cc.ll [ARM] Honor -mfloat-abi for libcall calling convention 2017-10-26 21:42:32 +00:00
intrinsics-coprocessor.ll ARM: Do not use llc -march in tests. 2017-08-01 22:20:49 +00:00
large-call.ll
large-stack.ll ARM: Do not use llc -march in tests. 2017-08-01 22:20:49 +00:00
ldr-str-imm12.ll Elide stores which are overwritten without being observed. 2017-05-16 19:43:56 +00:00
lit.local.cfg
longMACt.ll
lsr-deficiency.ll [Thumb] Select (CMPZ X, -C) -> (CMPZ (ADDS X, C), 0) 2016-09-09 12:52:24 +00:00
machine-licm.ll Make the canonicalisation on shifts benifit to more case. 2016-12-23 02:56:07 +00:00
mul_const.ll
pic-load.ll ARM: Add scheduling information for LDRLIT instructions to swift scheduling model 2015-07-17 23:18:26 +00:00
segmented-stacks.ll ARM: Do not use llc -march in tests. 2017-08-01 22:20:49 +00:00
setjmp_longjmp.ll Arm: Don't define a label twice with two setjmps in a function. 2015-07-16 22:34:20 +00:00
stack_guard_remat.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
t2sizereduction.mir [ARM] Register the Thumb2SizeReducePass. NFC 2017-12-19 12:19:08 +00:00
tail-call-r9.ll
tbb-removeadd.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
thumb2-adc.ll
thumb2-add.ll
thumb2-add2.ll
thumb2-add3.ll
thumb2-add4.ll
thumb2-add5.ll
thumb2-add6.ll
thumb2-and.ll
thumb2-and2.ll
thumb2-asr.ll
thumb2-asr2.ll
thumb2-bcc.ll
thumb2-bfc.ll
thumb2-bic.ll
thumb2-branch.ll
thumb2-call-tc.ll
thumb2-call.ll ARM: stop emitting blx instructions for most calls on MachO. 2016-05-10 19:17:47 +00:00
thumb2-cbnz.ll Codegen: Fix broken assumption in Tail Merge. 2016-06-24 18:16:36 +00:00
thumb2-clz.ll
thumb2-cmn.ll
thumb2-cmn2.ll [Thumb] Select (CMPZ X, -C) -> (CMPZ (ADDS X, C), 0) 2016-09-09 12:52:24 +00:00
thumb2-cmp.ll
thumb2-cpsr-liveness.ll Fix PR26655: Bail out if all regs of an inst BUNDLE have the correct kill flag 2016-05-10 17:57:27 +00:00
thumb2-eor.ll
thumb2-eor2.ll
thumb2-ifcvt1-tc.ll
thumb2-ifcvt1.ll CodeGen: If Convert blocks that would form a diamond when tail-merged. 2016-08-24 21:34:27 +00:00
thumb2-ifcvt2.ll [ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8). 2017-06-28 07:07:03 +00:00
thumb2-ifcvt3.ll
thumb2-jtb.ll [Thumb-1] Synthesize TBB/TBH instructions to make use of compressed jump tables 2016-11-01 13:37:41 +00:00
thumb2-ldm.ll [ARM] Generate consistent frame records for Thumb2 2016-08-23 09:19:22 +00:00
thumb2-ldr.ll
thumb2-ldr_ext.ll
thumb2-ldr_post.ll
thumb2-ldr_pre.ll
thumb2-ldrb.ll
thumb2-ldrd.ll
thumb2-ldrh.ll
thumb2-lsl.ll
thumb2-lsl2.ll
thumb2-lsr.ll
thumb2-lsr2.ll
thumb2-lsr3.ll
thumb2-mla.ll
thumb2-mls.ll
thumb2-mov.ll
thumb2-mul.ll
thumb2-mulhi.ll [ARM] Renaming +t2dsp feature into +dsp, as discussed on llvm-dev 2015-10-23 17:19:19 +00:00
thumb2-mvn.ll
thumb2-mvn2.ll
thumb2-neg.ll
thumb2-orn.ll
thumb2-orn2.ll
thumb2-orr.ll
thumb2-orr2.ll
thumb2-pack.ll [ARM] Remove t2xtpk feature from tests 2017-03-09 15:14:32 +00:00
thumb2-rev.ll [ARM] Remove t2xtpk feature from tests 2017-03-09 15:14:32 +00:00
thumb2-rev16.ll ARM: Do not use llc -march in tests. 2017-08-01 22:20:49 +00:00
thumb2-ror.ll
thumb2-rsb.ll
thumb2-rsb2.ll
thumb2-sbc.ll
thumb2-select.ll
thumb2-select_xform.ll
thumb2-shifter.ll
thumb2-smla.ll [ARM] Remove t2xtpk feature from tests 2017-03-09 15:14:32 +00:00
thumb2-smul.ll [ARM] Remove t2xtpk feature from tests 2017-03-09 15:14:32 +00:00
thumb2-spill-q.ll [ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions 2015-09-30 10:56:37 +00:00
thumb2-str.ll
thumb2-str_post.ll
thumb2-str_pre.ll
thumb2-strb.ll
thumb2-strh.ll
thumb2-sub.ll
thumb2-sub2.ll
thumb2-sub3.ll
thumb2-sub4.ll
thumb2-sub5.ll
thumb2-sxt-uxt.ll [ARM] Replace HasT2ExtractPack with HasDSP 2017-02-17 15:42:44 +00:00
thumb2-sxt_rot.ll [ARM] Replace HasT2ExtractPack with HasDSP 2017-02-17 15:42:44 +00:00
thumb2-tbb.ll [Thumb-1] Synthesize TBB/TBH instructions to make use of compressed jump tables 2016-11-01 13:37:41 +00:00
thumb2-tbh.ll [Thumb-1] Synthesize TBB/TBH instructions to make use of compressed jump tables 2016-11-01 13:37:41 +00:00
thumb2-teq.ll
thumb2-teq2.ll
thumb2-tst.ll
thumb2-tst2.ll
thumb2-uxt_rot.ll [ARM] Replace HasT2ExtractPack with HasDSP 2017-02-17 15:42:44 +00:00
thumb2-uxtb.ll [ARM] Replace HasT2ExtractPack with HasDSP 2017-02-17 15:42:44 +00:00
tls1.ll
tls2.ll Don't print (PLT) on arm. 2016-06-16 16:09:53 +00:00
tpsoft.ll ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets. 2015-04-23 20:31:26 +00:00
v8_IT_1.ll [ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions 2015-09-30 10:56:37 +00:00
v8_IT_2.ll
v8_IT_3.ll [arm] Fix Unnecessary reloads from GOT. 2017-11-13 20:45:38 +00:00
v8_IT_4.ll CodeGen: Allow small copyable blocks to "break" the CFG. 2017-01-31 23:48:32 +00:00
v8_IT_5.ll [Dominators] Include infinite loops in PostDominatorTree 2017-08-15 18:14:57 +00:00
v8_IT_6.ll