forked from OSchip/llvm-project
101 lines
4.4 KiB
LLVM
101 lines
4.4 KiB
LLVM
; RUN: opt -data-layout=A5 -S -mtriple=amdgcn-unknown-unknown -amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck -check-prefix=IR %s
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; RUN: llc -march=amdgcn -mcpu=fiji -disable-promote-alloca-to-vector < %s | FileCheck -check-prefix=ASM %s
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; IR-LABEL: define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 {
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; IR: alloca [5 x i32]
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; ASM-LABEL: {{^}}promote_alloca_shaders:
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; ASM: ; ScratchSize: 24
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define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 {
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entry:
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%stack = alloca [5 x i32], align 4, addrspace(5)
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%tmp0 = load i32, i32 addrspace(1)* %in, align 4
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%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp0
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store i32 4, i32 addrspace(5)* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
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%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
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store i32 5, i32 addrspace(5)* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
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%tmp2 = load i32, i32 addrspace(5)* %arrayidx4, align 4
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store i32 %tmp2, i32 addrspace(1)* %out, align 4
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%arrayidx5 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
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%tmp3 = load i32, i32 addrspace(5)* %arrayidx5
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%arrayidx6 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
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store i32 %tmp3, i32 addrspace(1)* %arrayidx6
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ret void
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}
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; OPT-LABEL: @promote_to_vector_call_c(
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; OPT-NOT: alloca
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; OPT: extractelement <2 x i32> %{{[0-9]+}}, i32 %in
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; ASM-LABEL: {{^}}promote_to_vector_call_c:
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; ASM-NOT: LDSByteSize
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; ASM: ; ScratchSize: 12
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define void @promote_to_vector_call_c(i32 addrspace(1)* %out, i32 %in) #0 {
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entry:
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%tmp = alloca [2 x i32], addrspace(5)
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%tmp1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
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%tmp2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
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store i32 0, i32 addrspace(5)* %tmp1
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store i32 1, i32 addrspace(5)* %tmp2
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%tmp3 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 %in
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%tmp4 = load i32, i32 addrspace(5)* %tmp3
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%tmp5 = load volatile i32, i32 addrspace(1)* undef
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%tmp6 = add i32 %tmp4, %tmp5
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store i32 %tmp6, i32 addrspace(1)* %out
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ret void
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}
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; OPT-LABEL: @no_promote_to_lds_c(
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; OPT: alloca
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; ASM-LABEL: {{^}}no_promote_to_lds_c:
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; ASM-NOT: LDSByteSize
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; ASM: ; ScratchSize: 24
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define void @no_promote_to_lds_c(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 {
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entry:
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%stack = alloca [5 x i32], align 4, addrspace(5)
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%0 = load i32, i32 addrspace(1)* %in, align 4
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%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %0
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store i32 4, i32 addrspace(5)* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
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%1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %1
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store i32 5, i32 addrspace(5)* %arrayidx3, align 4
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%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
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%2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
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store i32 %2, i32 addrspace(1)* %out, align 4
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%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
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%3 = load i32, i32 addrspace(5)* %arrayidx12
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%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
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store i32 %3, i32 addrspace(1)* %arrayidx13
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ret void
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}
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declare i32 @foo(i32 addrspace(5)*) #0
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; ASM-LABEL: {{^}}call_private:
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; ASM: buffer_store_dword
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; ASM: buffer_store_dword
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; ASM: s_swappc_b64
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; ASM: ScratchSize: 16396
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define amdgpu_kernel void @call_private(i32 addrspace(1)* %out, i32 %in) #0 {
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entry:
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%tmp = alloca [2 x i32], addrspace(5)
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%tmp1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
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%tmp2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
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store i32 0, i32 addrspace(5)* %tmp1
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store i32 1, i32 addrspace(5)* %tmp2
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%tmp3 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 %in
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%val = call i32 @foo(i32 addrspace(5)* %tmp3)
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind "amdgpu-max-work-group-size"="64" }
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attributes #1 = { nounwind readnone }
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