forked from OSchip/llvm-project
143 lines
5.7 KiB
LLVM
143 lines
5.7 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone
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declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>) nounwind readnone
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declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) nounwind readnone
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declare <16 x i64> @llvm.ctpop.v16i64(<16 x i64>) nounwind readnone
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; FUNC-LABEL: {{^}}s_ctpop_i64:
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; SI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; VI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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; GCN: s_bcnt1_i32_b64 [[SRESULT:s[0-9]+]], [[SVAL]]
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; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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; GCN: buffer_store_dword [[VRESULT]],
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; GCN: s_endpgm
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define void @s_ctpop_i64(i32 addrspace(1)* noalias %out, i64 %val) nounwind {
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%ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
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%truncctpop = trunc i64 %ctpop to i32
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store i32 %truncctpop, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_ctpop_i64:
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; GCN: buffer_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}},
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; GCN: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
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; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
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; VI-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
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; GCN: buffer_store_dword [[RESULT]],
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; GCN: s_endpgm
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define void @v_ctpop_i64(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind {
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%val = load i64, i64 addrspace(1)* %in, align 8
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%ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
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%truncctpop = trunc i64 %ctpop to i32
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store i32 %truncctpop, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FIXME: or 0 should be replaxed with copy
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; FUNC-LABEL: {{^}}v_ctpop_i64_user:
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; GCN: buffer_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}},
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; GCN: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
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; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
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; VI-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
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; GCN-DAG: v_or_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, [[RESULT]]
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; GCN-DAG: v_or_b32_e64 v[[RESULT_HI:[0-9]+]], 0, s{{[0-9]+}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}}
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; GCN: s_endpgm
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define void @v_ctpop_i64_user(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %s.val) nounwind {
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%val = load i64, i64 addrspace(1)* %in, align 8
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%ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
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%or = or i64 %ctpop, %s.val
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_ctpop_v2i64:
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; GCN: s_bcnt1_i32_b64
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; GCN: s_bcnt1_i32_b64
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; GCN: s_endpgm
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define void @s_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> %val) nounwind {
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%ctpop = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val) nounwind readnone
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%truncctpop = trunc <2 x i64> %ctpop to <2 x i32>
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store <2 x i32> %truncctpop, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_ctpop_v4i64:
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; GCN: s_bcnt1_i32_b64
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; GCN: s_bcnt1_i32_b64
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; GCN: s_bcnt1_i32_b64
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; GCN: s_bcnt1_i32_b64
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; GCN: s_endpgm
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define void @s_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> %val) nounwind {
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%ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
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%truncctpop = trunc <4 x i64> %ctpop to <4 x i32>
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store <4 x i32> %truncctpop, <4 x i32> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}v_ctpop_v2i64:
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: s_endpgm
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define void @v_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in) nounwind {
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%val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
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%ctpop = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val) nounwind readnone
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%truncctpop = trunc <2 x i64> %ctpop to <2 x i32>
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store <2 x i32> %truncctpop, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_ctpop_v4i64:
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: v_bcnt_u32_b32
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; GCN: s_endpgm
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define void @v_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> addrspace(1)* noalias %in) nounwind {
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%val = load <4 x i64>, <4 x i64> addrspace(1)* %in, align 32
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%ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
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%truncctpop = trunc <4 x i64> %ctpop to <4 x i32>
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store <4 x i32> %truncctpop, <4 x i32> addrspace(1)* %out, align 16
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ret void
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}
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; FIXME: We currently disallow SALU instructions in all branches,
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; but there are some cases when the should be allowed.
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; FUNC-LABEL: {{^}}ctpop_i64_in_br:
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; SI: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xd
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; VI: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x34
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; GCN: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]{{\]}}
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; GCN: v_mov_b32_e32 v[[VLO:[0-9]+]], [[RESULT]]
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; GCN: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[HIVAL]]
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; GCN: buffer_store_dwordx2 {{v\[}}[[VLO]]:[[VHI]]{{\]}}
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; GCN: s_endpgm
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define void @ctpop_i64_in_br(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %ctpop_arg, i32 %cond) {
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entry:
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%tmp0 = icmp eq i32 %cond, 0
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br i1 %tmp0, label %if, label %else
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if:
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%tmp2 = call i64 @llvm.ctpop.i64(i64 %ctpop_arg)
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br label %endif
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else:
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%tmp3 = getelementptr i64, i64 addrspace(1)* %in, i32 1
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%tmp4 = load i64, i64 addrspace(1)* %tmp3
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br label %endif
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endif:
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%tmp5 = phi i64 [%tmp2, %if], [%tmp4, %else]
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store i64 %tmp5, i64 addrspace(1)* %out
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ret void
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}
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