forked from OSchip/llvm-project
809 lines
26 KiB
C++
809 lines
26 KiB
C++
//===-- DisassemblerLLVM.cpp ------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "DisassemblerLLVM.h"
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#include "llvm-c/EnhancedDisassembly.h"
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#include "llvm/Support/TargetSelect.h"
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#include "lldb/Core/Address.h"
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#include "lldb/Core/DataExtractor.h"
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#include "lldb/Core/Disassembler.h"
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#include "lldb/Core/Module.h"
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#include "lldb/Core/PluginManager.h"
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#include "lldb/Core/Stream.h"
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#include "lldb/Core/StreamString.h"
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#include "lldb/Symbol/SymbolContext.h"
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#include "lldb/Target/ExecutionContext.h"
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#include "lldb/Target/Process.h"
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#include "lldb/Target/RegisterContext.h"
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#include "lldb/Target/Target.h"
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#include <assert.h>
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using namespace lldb;
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using namespace lldb_private;
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static int
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DataExtractorByteReader (uint8_t *byte, uint64_t address, void *arg)
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{
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DataExtractor &extractor = *((DataExtractor *)arg);
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if (extractor.ValidOffset(address))
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{
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*byte = *(extractor.GetDataStart() + address);
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return 0;
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}
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else
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{
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return -1;
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}
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}
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namespace {
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struct RegisterReaderArg {
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const lldb::addr_t instructionPointer;
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const EDDisassemblerRef disassembler;
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RegisterReaderArg(lldb::addr_t ip,
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EDDisassemblerRef dis) :
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instructionPointer(ip),
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disassembler(dis)
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{
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}
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};
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}
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static int IPRegisterReader(uint64_t *value, unsigned regID, void* arg)
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{
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uint64_t instructionPointer = ((RegisterReaderArg*)arg)->instructionPointer;
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EDDisassemblerRef disassembler = ((RegisterReaderArg*)arg)->disassembler;
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if (EDRegisterIsProgramCounter(disassembler, regID)) {
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*value = instructionPointer;
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return 0;
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}
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return -1;
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}
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InstructionLLVM::InstructionLLVM (const Address &addr,
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AddressClass addr_class,
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EDDisassemblerRef disassembler,
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llvm::Triple::ArchType arch_type) :
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Instruction (addr, addr_class),
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m_disassembler (disassembler),
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m_inst (NULL),
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m_arch_type (arch_type)
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{
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}
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InstructionLLVM::~InstructionLLVM()
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{
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if (m_inst)
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{
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EDReleaseInst(m_inst);
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m_inst = NULL;
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}
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}
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static void
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PadString(Stream *s, const std::string &str, size_t width)
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{
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int diff = width - str.length();
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if (diff > 0)
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s->Printf("%s%*.*s", str.c_str(), diff, diff, "");
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else
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s->Printf("%s ", str.c_str());
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}
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static void
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AddSymbolicInfo (ExecutionContextScope *exe_scope,
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StreamString &comment,
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uint64_t operand_value,
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const Address &inst_addr)
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{
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Address so_addr;
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Target *target = NULL;
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if (exe_scope)
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target = exe_scope->CalculateTarget();
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if (target && !target->GetSectionLoadList().IsEmpty())
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{
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if (target->GetSectionLoadList().ResolveLoadAddress(operand_value, so_addr))
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so_addr.Dump(&comment, exe_scope, Address::DumpStyleResolvedDescriptionNoModule, Address::DumpStyleSectionNameOffset);
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}
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else
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{
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Module *module = inst_addr.GetModule();
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if (module)
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{
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if (module->ResolveFileAddress(operand_value, so_addr))
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so_addr.Dump(&comment, exe_scope, Address::DumpStyleResolvedDescriptionNoModule, Address::DumpStyleSectionNameOffset);
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}
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}
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}
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#include "llvm/ADT/StringRef.h"
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static inline void StripSpaces(llvm::StringRef &Str)
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{
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while (!Str.empty() && isspace(Str[0]))
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Str = Str.substr(1);
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while (!Str.empty() && isspace(Str.back()))
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Str = Str.substr(0, Str.size()-1);
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}
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static inline void RStrip(llvm::StringRef &Str, char c)
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{
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if (!Str.empty() && Str.back() == c)
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Str = Str.substr(0, Str.size()-1);
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}
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// Aligns the raw disassembly (passed as 'str') with the rest of edis'ed disassembly output.
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// This is called from non-raw mode when edis of the current m_inst fails for some reason.
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static void
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Align(Stream *s, const char *str, size_t opcodeColWidth, size_t operandColWidth)
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{
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llvm::StringRef raw_disasm(str);
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StripSpaces(raw_disasm);
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// Split the raw disassembly into opcode and operands.
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std::pair<llvm::StringRef, llvm::StringRef> p = raw_disasm.split('\t');
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PadString(s, p.first, opcodeColWidth);
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if (!p.second.empty())
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PadString(s, p.second, operandColWidth);
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}
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#define AlignPC(pc_val) (pc_val & 0xFFFFFFFC)
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void
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InstructionLLVM::Dump
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(
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Stream *s,
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uint32_t max_opcode_byte_size,
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bool show_address,
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bool show_bytes,
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const lldb_private::ExecutionContext* exe_ctx,
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bool raw
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)
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{
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const size_t opcodeColumnWidth = 7;
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const size_t operandColumnWidth = 25;
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ExecutionContextScope *exe_scope = NULL;
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if (exe_ctx)
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exe_scope = exe_ctx->GetBestExecutionContextScope();
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// If we have an address, print it out
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if (GetAddress().IsValid() && show_address)
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{
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if (GetAddress().Dump (s,
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exe_scope,
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Address::DumpStyleLoadAddress,
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Address::DumpStyleModuleWithFileAddress,
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0))
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s->PutCString(": ");
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}
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// If we are supposed to show bytes, "bytes" will be non-NULL.
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if (show_bytes)
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{
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if (m_opcode.GetType() == Opcode::eTypeBytes)
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{
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// x86_64 and i386 are the only ones that use bytes right now so
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// pad out the byte dump to be able to always show 15 bytes (3 chars each)
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// plus a space
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if (max_opcode_byte_size > 0)
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m_opcode.Dump (s, max_opcode_byte_size * 3 + 1);
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else
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m_opcode.Dump (s, 15 * 3 + 1);
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}
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else
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{
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// Else, we have ARM which can show up to a uint32_t 0x00000000 (10 spaces)
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// plus two for padding...
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if (max_opcode_byte_size > 0)
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m_opcode.Dump (s, max_opcode_byte_size * 3 + 1);
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else
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m_opcode.Dump (s, 12);
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}
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}
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int numTokens = -1;
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// FIXME!!!
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/* Remove the following section of code related to force_raw .... */
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/*
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bool force_raw = m_arch_type == llvm::Triple::arm ||
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m_arch_type == llvm::Triple::thumb;
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if (!raw)
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raw = force_raw;
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*/
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/* .... when we fix the edis for arm/thumb. */
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if (!raw)
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numTokens = EDNumTokens(m_inst);
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int currentOpIndex = -1;
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bool printTokenized = false;
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if (numTokens != -1 && !raw)
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{
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addr_t base_addr = LLDB_INVALID_ADDRESS;
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uint32_t addr_nibble_size = 8;
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Target *target = NULL;
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if (exe_ctx)
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target = exe_ctx->GetTargetPtr();
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if (target)
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{
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if (!target->GetSectionLoadList().IsEmpty())
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base_addr = GetAddress().GetLoadAddress (target);
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addr_nibble_size = target->GetArchitecture().GetAddressByteSize() * 2;
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}
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if (base_addr == LLDB_INVALID_ADDRESS)
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base_addr = GetAddress().GetFileAddress ();
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lldb::addr_t PC = base_addr + EDInstByteSize(m_inst);
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// When executing an ARM instruction, PC reads as the address of the
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// current instruction plus 8. And for Thumb, it is plus 4.
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if (m_arch_type == llvm::Triple::arm)
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PC = base_addr + 8;
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else if (m_arch_type == llvm::Triple::thumb)
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PC = base_addr + 4;
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RegisterReaderArg rra(PC, m_disassembler);
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printTokenized = true;
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// Handle the opcode column.
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StreamString opcode;
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int tokenIndex = 0;
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EDTokenRef token;
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const char *tokenStr;
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if (EDGetToken(&token, m_inst, tokenIndex)) // 0 on success
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printTokenized = false;
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else if (!EDTokenIsOpcode(token))
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printTokenized = false;
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else if (EDGetTokenString(&tokenStr, token)) // 0 on success
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printTokenized = false;
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if (printTokenized)
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{
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// Put the token string into our opcode string
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opcode.PutCString(tokenStr);
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// If anything follows, it probably starts with some whitespace. Skip it.
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if (++tokenIndex < numTokens)
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{
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if (EDGetToken(&token, m_inst, tokenIndex)) // 0 on success
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printTokenized = false;
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else if (!EDTokenIsWhitespace(token))
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printTokenized = false;
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}
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++tokenIndex;
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}
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// Handle the operands and the comment.
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StreamString operands;
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StreamString comment;
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if (printTokenized)
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{
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bool show_token = false;
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for (; tokenIndex < numTokens; ++tokenIndex)
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{
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if (EDGetToken(&token, m_inst, tokenIndex))
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return;
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int operandIndex = EDOperandIndexForToken(token);
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if (operandIndex >= 0)
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{
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if (operandIndex != currentOpIndex)
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{
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show_token = true;
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currentOpIndex = operandIndex;
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EDOperandRef operand;
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if (!EDGetOperand(&operand, m_inst, currentOpIndex))
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{
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if (EDOperandIsMemory(operand))
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{
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uint64_t operand_value;
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if (!EDEvaluateOperand(&operand_value, operand, IPRegisterReader, &rra))
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{
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if (EDInstIsBranch(m_inst))
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{
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operands.Printf("0x%*.*llx ", addr_nibble_size, addr_nibble_size, operand_value);
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show_token = false;
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}
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else
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{
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// Put the address value into the comment
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comment.Printf("0x%*.*llx ", addr_nibble_size, addr_nibble_size, operand_value);
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}
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AddSymbolicInfo(exe_scope, comment, operand_value, GetAddress());
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} // EDEvaluateOperand
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} // EDOperandIsMemory
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} // EDGetOperand
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} // operandIndex != currentOpIndex
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} // operandIndex >= 0
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if (show_token)
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{
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if (EDGetTokenString(&tokenStr, token))
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{
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printTokenized = false;
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break;
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}
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operands.PutCString(tokenStr);
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}
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} // for (tokenIndex)
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// FIXME!!!
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// Workaround for llvm::tB's operands not properly parsed by ARMAsmParser.
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if (m_arch_type == llvm::Triple::thumb && opcode.GetString() == "b") {
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const char *inst_str;
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const char *pos = NULL;
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operands.Clear(); comment.Clear();
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if (EDGetInstString(&inst_str, m_inst) == 0 && (pos = strstr(inst_str, "#")) != NULL) {
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uint64_t operand_value = PC + atoi(++pos);
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// Put the address value into the operands.
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operands.Printf("0x%8.8llx ", operand_value);
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AddSymbolicInfo(exe_scope, comment, operand_value, GetAddress());
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}
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}
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// Yet more workaround for "bl #..." and "blx #...".
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if ((m_arch_type == llvm::Triple::arm || m_arch_type == llvm::Triple::thumb) &&
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(opcode.GetString() == "bl" || opcode.GetString() == "blx")) {
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const char *inst_str;
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const char *pos = NULL;
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operands.Clear(); comment.Clear();
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if (EDGetInstString(&inst_str, m_inst) == 0 && (pos = strstr(inst_str, "#")) != NULL) {
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if (m_arch_type == llvm::Triple::thumb && opcode.GetString() == "blx") {
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// A8.6.23 BLX (immediate)
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// Target Address = Align(PC,4) + offset value
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PC = AlignPC(PC);
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}
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uint64_t operand_value = PC + atoi(++pos);
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// Put the address value into the comment.
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comment.Printf("0x%8.8llx ", operand_value);
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// And the original token string into the operands.
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llvm::StringRef Str(pos - 1);
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RStrip(Str, '\n');
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operands.PutCString(Str.str().c_str());
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AddSymbolicInfo(exe_scope, comment, operand_value, GetAddress());
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}
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}
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// END of workaround.
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// If both operands and comment are empty, we will just print out
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// the raw disassembly.
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if (operands.GetString().empty() && comment.GetString().empty())
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{
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const char *str;
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if (EDGetInstString(&str, m_inst))
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return;
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Align(s, str, opcodeColumnWidth, operandColumnWidth);
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}
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else
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{
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PadString(s, opcode.GetString(), opcodeColumnWidth);
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if (comment.GetString().empty())
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s->PutCString(operands.GetString().c_str());
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else
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{
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PadString(s, operands.GetString(), operandColumnWidth);
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s->PutCString("; ");
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s->PutCString(comment.GetString().c_str());
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} // else (comment.GetString().empty())
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} // else (operands.GetString().empty() && comment.GetString().empty())
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} // printTokenized
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} // numTokens != -1
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if (!printTokenized)
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{
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const char *str;
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if (EDGetInstString(&str, m_inst)) // 0 on success
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return;
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if (raw)
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s->Write(str, strlen(str) - 1);
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else
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{
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// EDis fails to parse the tokens of this inst. Need to align this
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// raw disassembly's opcode with the rest of output.
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Align(s, str, opcodeColumnWidth, operandColumnWidth);
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}
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}
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}
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void
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InstructionLLVM::CalculateMnemonic (ExecutionContextScope *exe_scope)
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{
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const int num_tokens = EDNumTokens(m_inst);
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if (num_tokens > 0)
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{
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const char *token_cstr = NULL;
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int currentOpIndex = -1;
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StreamString comment;
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uint32_t addr_nibble_size = 8;
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addr_t base_addr = LLDB_INVALID_ADDRESS;
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Target *target = NULL;
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if (exe_scope)
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target = exe_scope->CalculateTarget();
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if (target && !target->GetSectionLoadList().IsEmpty())
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base_addr = GetAddress().GetLoadAddress (target);
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if (base_addr == LLDB_INVALID_ADDRESS)
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base_addr = GetAddress().GetFileAddress ();
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addr_nibble_size = target->GetArchitecture().GetAddressByteSize() * 2;
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lldb::addr_t PC = base_addr + EDInstByteSize(m_inst);
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// When executing an ARM instruction, PC reads as the address of the
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// current instruction plus 8. And for Thumb, it is plus 4.
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if (m_arch_type == llvm::Triple::arm)
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PC = base_addr + 8;
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else if (m_arch_type == llvm::Triple::thumb)
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PC = base_addr + 4;
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RegisterReaderArg rra(PC, m_disassembler);
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for (int token_idx = 0; token_idx < num_tokens; ++token_idx)
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{
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EDTokenRef token;
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if (EDGetToken(&token, m_inst, token_idx))
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break;
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if (EDTokenIsOpcode(token) == 1)
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{
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if (EDGetTokenString(&token_cstr, token) == 0) // 0 on success
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{
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if (token_cstr)
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m_opcode_name.assign(token_cstr);
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}
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}
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else
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{
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int operandIndex = EDOperandIndexForToken(token);
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if (operandIndex >= 0)
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{
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if (operandIndex != currentOpIndex)
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{
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currentOpIndex = operandIndex;
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EDOperandRef operand;
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if (!EDGetOperand(&operand, m_inst, currentOpIndex))
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{
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if (EDOperandIsMemory(operand))
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{
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uint64_t operand_value;
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if (!EDEvaluateOperand(&operand_value, operand, IPRegisterReader, &rra))
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{
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comment.Printf("0x%*.*llx ", addr_nibble_size, addr_nibble_size, operand_value);
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AddSymbolicInfo (exe_scope, comment, operand_value, GetAddress());
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}
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}
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}
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}
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}
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if (m_mnemocics.empty() && EDTokenIsWhitespace (token) == 1)
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continue;
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if (EDGetTokenString (&token_cstr, token))
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break;
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m_mnemocics.append (token_cstr);
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}
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}
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// FIXME!!!
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// Workaround for llvm::tB's operands not properly parsed by ARMAsmParser.
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if (m_arch_type == llvm::Triple::thumb && m_opcode_name.compare("b") == 0)
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{
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const char *inst_str;
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const char *pos = NULL;
|
|
comment.Clear();
|
|
if (EDGetInstString(&inst_str, m_inst) == 0 && (pos = strstr(inst_str, "#")) != NULL)
|
|
{
|
|
uint64_t operand_value = PC + atoi(++pos);
|
|
// Put the address value into the operands.
|
|
comment.Printf("0x%*.*llx ", addr_nibble_size, addr_nibble_size, operand_value);
|
|
AddSymbolicInfo (exe_scope, comment, operand_value, GetAddress());
|
|
}
|
|
}
|
|
// Yet more workaround for "bl #..." and "blx #...".
|
|
if ((m_arch_type == llvm::Triple::arm || m_arch_type == llvm::Triple::thumb) &&
|
|
(m_opcode_name.compare("bl") == 0 || m_opcode_name.compare("blx") == 0))
|
|
{
|
|
const char *inst_str;
|
|
const char *pos = NULL;
|
|
comment.Clear();
|
|
if (EDGetInstString(&inst_str, m_inst) == 0 && (pos = strstr(inst_str, "#")) != NULL)
|
|
{
|
|
if (m_arch_type == llvm::Triple::thumb && m_opcode_name.compare("blx") == 0)
|
|
{
|
|
// A8.6.23 BLX (immediate)
|
|
// Target Address = Align(PC,4) + offset value
|
|
PC = AlignPC(PC);
|
|
}
|
|
uint64_t operand_value = PC + atoi(++pos);
|
|
// Put the address value into the comment.
|
|
comment.Printf("0x%*.*llx ", addr_nibble_size, addr_nibble_size, operand_value);
|
|
// And the original token string into the operands.
|
|
// llvm::StringRef Str(pos - 1);
|
|
// RStrip(Str, '\n');
|
|
// operands.PutCString(Str.str().c_str());
|
|
AddSymbolicInfo (exe_scope, comment, operand_value, GetAddress());
|
|
}
|
|
}
|
|
// END of workaround.
|
|
|
|
m_comment.swap (comment.GetString());
|
|
}
|
|
}
|
|
|
|
void
|
|
InstructionLLVM::CalculateOperands(ExecutionContextScope *exe_scope)
|
|
{
|
|
// Do all of the work in CalculateMnemonic()
|
|
CalculateMnemonic (exe_scope);
|
|
}
|
|
|
|
void
|
|
InstructionLLVM::CalculateComment(ExecutionContextScope *exe_scope)
|
|
{
|
|
// Do all of the work in CalculateMnemonic()
|
|
CalculateMnemonic (exe_scope);
|
|
}
|
|
|
|
bool
|
|
InstructionLLVM::DoesBranch() const
|
|
{
|
|
return EDInstIsBranch(m_inst);
|
|
}
|
|
|
|
size_t
|
|
InstructionLLVM::Decode (const Disassembler &disassembler,
|
|
const lldb_private::DataExtractor &data,
|
|
uint32_t data_offset)
|
|
{
|
|
if (EDCreateInsts(&m_inst, 1, m_disassembler, DataExtractorByteReader, data_offset, (void*)(&data)))
|
|
{
|
|
const int byte_size = EDInstByteSize(m_inst);
|
|
uint32_t offset = data_offset;
|
|
// Make a copy of the opcode in m_opcode
|
|
switch (disassembler.GetArchitecture().GetMachine())
|
|
{
|
|
case llvm::Triple::x86:
|
|
case llvm::Triple::x86_64:
|
|
m_opcode.SetOpcodeBytes (data.PeekData (data_offset, byte_size), byte_size);
|
|
break;
|
|
|
|
case llvm::Triple::arm:
|
|
case llvm::Triple::thumb:
|
|
switch (byte_size)
|
|
{
|
|
case 2:
|
|
m_opcode.SetOpcode16 (data.GetU16 (&offset));
|
|
break;
|
|
|
|
case 4:
|
|
{
|
|
if (GetAddressClass() == eAddressClassCodeAlternateISA)
|
|
{
|
|
// If it is a 32-bit THUMB instruction, we need to swap the upper & lower halves.
|
|
uint32_t orig_bytes = data.GetU32 (&offset);
|
|
uint16_t upper_bits = (orig_bytes >> 16) & ((1u << 16) - 1);
|
|
uint16_t lower_bits = orig_bytes & ((1u << 16) - 1);
|
|
uint32_t swapped = (lower_bits << 16) | upper_bits;
|
|
m_opcode.SetOpcode32 (swapped);
|
|
}
|
|
else
|
|
m_opcode.SetOpcode32 (data.GetU32 (&offset));
|
|
}
|
|
break;
|
|
|
|
default:
|
|
assert (!"Invalid ARM opcode size");
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
assert (!"This shouldn't happen since we control the architecture we allow DisassemblerLLVM to be created for");
|
|
break;
|
|
}
|
|
return byte_size;
|
|
}
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
static inline EDAssemblySyntax_t
|
|
SyntaxForArchSpec (const ArchSpec &arch)
|
|
{
|
|
switch (arch.GetMachine ())
|
|
{
|
|
case llvm::Triple::x86:
|
|
case llvm::Triple::x86_64:
|
|
return kEDAssemblySyntaxX86ATT;
|
|
case llvm::Triple::arm:
|
|
case llvm::Triple::thumb:
|
|
return kEDAssemblySyntaxARMUAL;
|
|
default:
|
|
break;
|
|
}
|
|
return (EDAssemblySyntax_t)0; // default
|
|
}
|
|
|
|
Disassembler *
|
|
DisassemblerLLVM::CreateInstance(const ArchSpec &arch)
|
|
{
|
|
std::auto_ptr<DisassemblerLLVM> disasm_ap (new DisassemblerLLVM(arch));
|
|
|
|
if (disasm_ap.get() && disasm_ap->IsValid())
|
|
return disasm_ap.release();
|
|
|
|
return NULL;
|
|
}
|
|
|
|
DisassemblerLLVM::DisassemblerLLVM(const ArchSpec &arch) :
|
|
Disassembler (arch),
|
|
m_disassembler (NULL),
|
|
m_disassembler_thumb (NULL) // For ARM only
|
|
{
|
|
// Initialize the LLVM objects needed to use the disassembler.
|
|
static struct InitializeLLVM {
|
|
InitializeLLVM() {
|
|
llvm::InitializeAllTargetInfos();
|
|
llvm::InitializeAllTargetMCs();
|
|
llvm::InitializeAllAsmParsers();
|
|
llvm::InitializeAllDisassemblers();
|
|
}
|
|
} InitializeLLVM;
|
|
|
|
const std::string &arch_triple = arch.GetTriple().str();
|
|
if (!arch_triple.empty())
|
|
{
|
|
if (EDGetDisassembler(&m_disassembler, arch_triple.c_str(), SyntaxForArchSpec (arch)))
|
|
m_disassembler = NULL;
|
|
llvm::Triple::ArchType llvm_arch = arch.GetTriple().getArch();
|
|
// Don't have the lldb::Triple::thumb architecture here. If someone specifies
|
|
// "thumb" as the architecture, we want a thumb only disassembler. But if any
|
|
// architecture starting with "arm" if specified, we want to auto detect the
|
|
// arm/thumb code automatically using the AddressClass from section offset
|
|
// addresses.
|
|
if (llvm_arch == llvm::Triple::arm)
|
|
{
|
|
if (EDGetDisassembler(&m_disassembler_thumb, "thumbv7-apple-darwin", kEDAssemblySyntaxARMUAL))
|
|
m_disassembler_thumb = NULL;
|
|
}
|
|
}
|
|
}
|
|
|
|
DisassemblerLLVM::~DisassemblerLLVM()
|
|
{
|
|
}
|
|
|
|
size_t
|
|
DisassemblerLLVM::DecodeInstructions
|
|
(
|
|
const Address &base_addr,
|
|
const DataExtractor& data,
|
|
uint32_t data_offset,
|
|
uint32_t num_instructions,
|
|
bool append
|
|
)
|
|
{
|
|
if (m_disassembler == NULL)
|
|
return 0;
|
|
|
|
size_t total_inst_byte_size = 0;
|
|
|
|
if (!append)
|
|
m_instruction_list.Clear();
|
|
|
|
while (data.ValidOffset(data_offset) && num_instructions)
|
|
{
|
|
Address inst_addr (base_addr);
|
|
inst_addr.Slide(data_offset);
|
|
|
|
bool use_thumb = false;
|
|
// If we have a thumb disassembler, then we have an ARM architecture
|
|
// so we need to check what the instruction address class is to make
|
|
// sure we shouldn't be disassembling as thumb...
|
|
AddressClass inst_address_class = eAddressClassInvalid;
|
|
if (m_disassembler_thumb)
|
|
{
|
|
inst_address_class = inst_addr.GetAddressClass ();
|
|
if (inst_address_class == eAddressClassCodeAlternateISA)
|
|
use_thumb = true;
|
|
}
|
|
|
|
InstructionSP inst_sp (new InstructionLLVM (inst_addr,
|
|
inst_address_class,
|
|
use_thumb ? m_disassembler_thumb : m_disassembler,
|
|
use_thumb ? llvm::Triple::thumb : m_arch.GetMachine()));
|
|
|
|
size_t inst_byte_size = inst_sp->Decode (*this, data, data_offset);
|
|
|
|
if (inst_byte_size == 0)
|
|
break;
|
|
|
|
m_instruction_list.Append (inst_sp);
|
|
|
|
total_inst_byte_size += inst_byte_size;
|
|
data_offset += inst_byte_size;
|
|
num_instructions--;
|
|
}
|
|
|
|
return total_inst_byte_size;
|
|
}
|
|
|
|
void
|
|
DisassemblerLLVM::Initialize()
|
|
{
|
|
PluginManager::RegisterPlugin (GetPluginNameStatic(),
|
|
GetPluginDescriptionStatic(),
|
|
CreateInstance);
|
|
}
|
|
|
|
void
|
|
DisassemblerLLVM::Terminate()
|
|
{
|
|
PluginManager::UnregisterPlugin (CreateInstance);
|
|
}
|
|
|
|
|
|
const char *
|
|
DisassemblerLLVM::GetPluginNameStatic()
|
|
{
|
|
return "llvm";
|
|
}
|
|
|
|
const char *
|
|
DisassemblerLLVM::GetPluginDescriptionStatic()
|
|
{
|
|
return "Disassembler that uses LLVM opcode tables to disassemble i386, x86_64 and ARM.";
|
|
}
|
|
|
|
//------------------------------------------------------------------
|
|
// PluginInterface protocol
|
|
//------------------------------------------------------------------
|
|
const char *
|
|
DisassemblerLLVM::GetPluginName()
|
|
{
|
|
return "DisassemblerLLVM";
|
|
}
|
|
|
|
const char *
|
|
DisassemblerLLVM::GetShortPluginName()
|
|
{
|
|
return GetPluginNameStatic();
|
|
}
|
|
|
|
uint32_t
|
|
DisassemblerLLVM::GetPluginVersion()
|
|
{
|
|
return 1;
|
|
}
|
|
|