forked from OSchip/llvm-project
298 lines
10 KiB
LLVM
298 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX
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; First, check the generic pattern for any 2 vector constants. Then, check special cases where
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; the constants are all off-by-one. Finally, check the extra special cases where the constants
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; include 0 or -1.
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; Each minimal select test is repeated with a more typical pattern that includes a compare to
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; generate the condition value.
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; TODO: If we don't have blendv, this can definitely be improved. There's also a selection of
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; chips where it makes sense to transform the general case blendv to 2 bit-ops. That should be
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; a uarch-specfic transform. At some point (Ryzen?), the implementation should catch up to the
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; architecture, so blendv is as fast as a single bit-op.
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define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) {
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; SSE-LABEL: sel_C1_or_C2_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: pslld $31, %xmm0
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; SSE-NEXT: psrad $31, %xmm0
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: pandn {{.*}}(%rip), %xmm1
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: por %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sel_C1_or_C2_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vpslld $31, %xmm0, %xmm0
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; AVX-NEXT: vmovaps {{.*#+}} xmm1 = [42,0,4294967294,4294967295]
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; AVX-NEXT: vblendvps %xmm0, {{.*}}(%rip), %xmm1, %xmm0
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; AVX-NEXT: retq
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%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: cmp_sel_C1_or_C2_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: pandn {{.*}}(%rip), %xmm1
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: por %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: cmp_sel_C1_or_C2_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovaps {{.*#+}} xmm1 = [42,0,4294967294,4294967295]
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; AVX-NEXT: vblendvps %xmm0, {{.*}}(%rip), %xmm1, %xmm0
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; AVX-NEXT: retq
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
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ret <4 x i32> %add
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}
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define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) {
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; SSE-LABEL: sel_Cplus1_or_C_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sel_Cplus1_or_C_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: cmp_sel_Cplus1_or_C_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE-NEXT: movdqa {{.*#+}} xmm1 = [42,0,4294967294,4294967295]
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; SSE-NEXT: psubd %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: cmp_sel_Cplus1_or_C_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [42,0,4294967294,4294967295]
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; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
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ret <4 x i32> %add
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}
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define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {
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; SSE-LABEL: sel_Cminus1_or_C_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: pslld $31, %xmm0
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; SSE-NEXT: psrad $31, %xmm0
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sel_Cminus1_or_C_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vpslld $31, %xmm0, %xmm0
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; AVX-NEXT: vpsrad $31, %xmm0, %xmm0
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; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: cmp_sel_Cminus1_or_C_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: cmp_sel_Cminus1_or_C_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
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ret <4 x i32> %add
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}
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define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) {
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; SSE-LABEL: sel_minus1_or_0_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: pslld $31, %xmm0
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; SSE-NEXT: psrad $31, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sel_minus1_or_0_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vpslld $31, %xmm0, %xmm0
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; AVX-NEXT: vpsrad $31, %xmm0, %xmm0
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; AVX-NEXT: retq
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%add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: cmp_sel_minus1_or_0_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: cmp_sel_minus1_or_0_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %add
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}
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define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {
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; SSE-LABEL: sel_0_or_minus1_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE-NEXT: paddd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sel_0_or_minus1_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: cmp_sel_0_or_minus1_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE-NEXT: pxor %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: cmp_sel_0_or_minus1_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %add
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}
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define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) {
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; SSE-LABEL: sel_1_or_0_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sel_1_or_0_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: cmp_sel_1_or_0_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE-NEXT: psrld $31, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: cmp_sel_1_or_0_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpsrld $31, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %add
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}
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define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) {
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; SSE-LABEL: sel_0_or_1_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: andnps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sel_0_or_1_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vandnps {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) {
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; SSE-LABEL: cmp_sel_0_or_1_vec:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE-NEXT: pandn {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: cmp_sel_0_or_1_vec:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpandn {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %add
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}
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; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=21167
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define <2 x i37> @ossfuzz21167(<2 x i37> %x, <2 x i37> %y) {
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; SSE-LABEL: ossfuzz21167:
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; SSE: # %bb.0: # %BB
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; SSE-NEXT: psllq $27, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: psrad $27, %xmm0
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
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; SSE-NEXT: psrlq $27, %xmm1
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; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
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; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
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; SSE-NEXT: pxor %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: pcmpgtd %xmm0, %xmm2
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; SSE-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; SSE-NEXT: pand %xmm2, %xmm1
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
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; SSE-NEXT: por %xmm1, %xmm0
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: ossfuzz21167:
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; AVX: # %bb.0: # %BB
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; AVX-NEXT: vpsllq $27, %xmm1, %xmm0
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; AVX-NEXT: vpsrad $27, %xmm0, %xmm1
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; AVX-NEXT: vpsrlq $27, %xmm0, %xmm0
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; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
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; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpsrlq $63, %xmm0, %xmm0
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; AVX-NEXT: retq
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BB:
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%c0 = icmp sgt <2 x i37> %y, zeroinitializer
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%xor_x = xor <2 x i37> undef, undef
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%smax96 = select <2 x i1> %c0, <2 x i37> %xor_x, <2 x i37> zeroinitializer
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ret <2 x i37> %smax96
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}
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