Jessica Paquette 26fb036559 [GlobalISel] Implement computeNumSignBits for G_ASSERT_SEXT ... Same implementation as G_SEXT_INREG. Add a testcase to combine-sext-inreg for a concrete example, and a testcase to KnownBitsTest. Differential Revision: https://reviews.llvm.org/D96897		2021-02-17 13:53:17 -08:00
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AArch64	[GlobalISel] Add G_ASSERT_SEXT	2021-02-17 13:10:34 -08:00
AMDGPU	[GlobalISel] Implement computeNumSignBits for G_ASSERT_SEXT	2021-02-17 13:53:17 -08:00
ARC	…
ARM	[LSR] Add a flag that overrides the target's preferred addressing mode	2021-02-17 16:50:21 +00:00
AVR	[AVR] Fix a bug in 16-bit shifts	2021-02-14 11:54:55 +08:00
BPF	…
Generic	[CodeGen] New pass: Replace vector intrinsics with call to vector library	2021-02-12 12:53:27 -05:00
Hexagon	[NewPM][opt] Run the "default" AA pipeline by default	2021-01-21 21:08:54 -08:00
Inputs	…
Lanai	…
MIR	[AMDGPU] Implement mir parseCustomPseudoSourceValue	2021-01-22 11:24:08 +01:00
MSP430	…
Mips	[DAGCombiner] Remove (sra (shl X, C), C) if X has more than C sign bits.	2021-02-03 10:18:40 -08:00
NVPTX	[NVPTX][NewPM] Re-enable NVVMReflectPass	2021-02-08 13:58:17 -08:00
PowerPC	[PowerPC][AIX] Enable Shrinkwrapping on 32 and 64 bit AIX.	2021-02-17 14:54:57 +00:00
RISCV	[RISCV] Add support for fixed vector vselect	2021-02-17 10:59:00 +00:00
SPARC	[SPARC] Fix fp128 load/stores	2021-01-13 14:59:50 -08:00
SystemZ	[SystemZ] Separate LoZ ELF specifics in tablegen.	2021-02-17 16:11:58 -05:00
Thumb	[RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer	2021-01-23 09:10:03 +00:00
Thumb2	[ARM] Use rGPR for writeback vldrs	2021-02-16 16:44:47 +00:00
VE	[VE] Update VELIntrinsic tests	2021-01-13 00:12:50 +09:00
WebAssembly	[WebAssemblly] Fix EHPadStack update in fixCallUnwindMismatches	2021-02-17 12:14:11 -08:00
WinCFGuard	…
WinEH	…
X86	[DAG] Fold shuffle(bop(shuffle(x,y),shuffle(z,w)),bop(shuffle(a,b),shuffle(c,d))) (REAPPLIED)	2021-02-17 11:42:43 +00:00
XCore	…