forked from OSchip/llvm-project
77 lines
2.1 KiB
LLVM
77 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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; The easy case: a constant power-of-2 divisor.
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define i64 @const_pow_2(i64 %x) {
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; CHECK-LABEL: const_pow_2:
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; CHECK: # BB#0:
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; CHECK-NEXT: andl $31, %edi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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%urem = urem i64 %x, 32
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ret i64 %urem
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}
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; A left-shifted power-of-2 divisor. Use a weird type for wider coverage.
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define i25 @shift_left_pow_2(i25 %x, i25 %y) {
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; CHECK-LABEL: shift_left_pow_2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: shll %cl, %eax
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; CHECK-NEXT: addl $33554431, %eax # imm = 0x1FFFFFF
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; CHECK-NEXT: andl %edi, %eax
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; CHECK-NEXT: retq
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%shl = shl i25 1, %y
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%urem = urem i25 %x, %shl
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ret i25 %urem
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}
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; A logically right-shifted sign bit is a power-of-2 or UB.
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define i16 @shift_right_pow_2(i16 %x, i16 %y) {
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; CHECK-LABEL: shift_right_pow_2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl $32768, %eax # imm = 0x8000
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: shrl %cl, %eax
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; CHECK-NEXT: decl %eax
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; CHECK-NEXT: andl %edi, %eax
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; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; CHECK-NEXT: retq
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%shr = lshr i16 -32768, %y
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%urem = urem i16 %x, %shr
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ret i16 %urem
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}
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; FIXME: A zero divisor would be UB, so this could be reduced to an 'and' with 3.
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define i8 @and_pow_2(i8 %x, i8 %y) {
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; CHECK-LABEL: and_pow_2:
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; CHECK: # BB#0:
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; CHECK-NEXT: andb $4, %sil
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
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; CHECK-NEXT: divb %sil
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; CHECK-NEXT: movzbl %ah, %eax # NOREX
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; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; CHECK-NEXT: retq
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%and = and i8 %y, 4
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%urem = urem i8 %x, %and
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ret i8 %urem
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}
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; A vector splat constant divisor should get the same treatment as a scalar.
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define <4 x i32> @vec_const_pow_2(<4 x i32> %x) {
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; CHECK-LABEL: vec_const_pow_2:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%urem = urem <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
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ret <4 x i32> %urem
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}
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