forked from OSchip/llvm-project
217 lines
7.2 KiB
C++
217 lines
7.2 KiB
C++
//===-- AMDGPUBaseInfo.h - Top level definitions for AMDGPU -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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#include "AMDKernelCodeT.h"
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#include "llvm/IR/CallingConv.h"
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#include "SIDefines.h"
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#define GET_INSTRINFO_OPERAND_ENUM
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#include "AMDGPUGenInstrInfo.inc"
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#undef GET_INSTRINFO_OPERAND_ENUM
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namespace llvm {
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class FeatureBitset;
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class Function;
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class GlobalValue;
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class MCContext;
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class MCInstrDesc;
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class MCRegisterClass;
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class MCRegisterInfo;
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class MCSection;
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class MCSubtargetInfo;
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namespace AMDGPU {
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LLVM_READONLY
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int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
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struct IsaVersion {
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unsigned Major;
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unsigned Minor;
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unsigned Stepping;
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};
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IsaVersion getIsaVersion(const FeatureBitset &Features);
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void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
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const FeatureBitset &Features);
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MCSection *getHSATextSection(MCContext &Ctx);
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MCSection *getHSADataGlobalAgentSection(MCContext &Ctx);
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MCSection *getHSADataGlobalProgramSection(MCContext &Ctx);
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MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx);
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bool isGroupSegment(const GlobalValue *GV);
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bool isGlobalSegment(const GlobalValue *GV);
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bool isReadOnlySegment(const GlobalValue *GV);
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/// \returns True if constants should be emitted to .text section for given
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/// target triple \p TT, false otherwise.
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bool shouldEmitConstantsToTextSection(const Triple &TT);
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/// \returns Integer value requested using \p F's \p Name attribute.
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///
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/// \returns \p Default if attribute is not present.
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///
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/// \returns \p Default and emits error if requested value cannot be converted
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/// to integer.
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int getIntegerAttribute(const Function &F, StringRef Name, int Default);
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/// \returns A pair of integer values requested using \p F's \p Name attribute
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/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
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/// is false).
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///
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/// \returns \p Default if attribute is not present.
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///
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/// \returns \p Default and emits error if one of the requested values cannot be
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/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
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/// not present.
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std::pair<int, int> getIntegerPairAttribute(const Function &F,
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StringRef Name,
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std::pair<int, int> Default,
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bool OnlyFirstRequired = false);
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/// \returns Waitcnt bit mask for given isa \p Version.
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unsigned getWaitcntBitMask(IsaVersion Version);
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/// \returns Vmcnt bit mask for given isa \p Version.
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unsigned getVmcntBitMask(IsaVersion Version);
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/// \returns Expcnt bit mask for given isa \p Version.
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unsigned getExpcntBitMask(IsaVersion Version);
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/// \returns Lgkmcnt bit mask for given isa \p Version.
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unsigned getLgkmcntBitMask(IsaVersion Version);
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/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
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unsigned decodeVmcnt(IsaVersion Version, unsigned Waitcnt);
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/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
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unsigned decodeExpcnt(IsaVersion Version, unsigned Waitcnt);
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/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
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unsigned decodeLgkmcnt(IsaVersion Version, unsigned Waitcnt);
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/// \brief Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
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/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
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/// \p Lgkmcnt respectively.
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///
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/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
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/// \p Vmcnt = \p Waitcnt[3:0]
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/// \p Expcnt = \p Waitcnt[6:4]
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/// \p Lgkmcnt = \p Waitcnt[11:8]
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void decodeWaitcnt(IsaVersion Version, unsigned Waitcnt,
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unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
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/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
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unsigned encodeVmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Vmcnt);
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/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
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unsigned encodeExpcnt(IsaVersion Version, unsigned Waitcnt, unsigned Expcnt);
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/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
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unsigned encodeLgkmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Lgkmcnt);
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/// \brief Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
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/// \p Version.
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///
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/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
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/// Waitcnt[3:0] = \p Vmcnt
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/// Waitcnt[6:4] = \p Expcnt
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/// Waitcnt[11:8] = \p Lgkmcnt
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///
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/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
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/// isa \p Version.
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unsigned encodeWaitcnt(IsaVersion Version,
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unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
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unsigned getInitialPSInputAddr(const Function &F);
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bool isShader(CallingConv::ID cc);
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bool isCompute(CallingConv::ID cc);
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bool isSI(const MCSubtargetInfo &STI);
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bool isCI(const MCSubtargetInfo &STI);
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bool isVI(const MCSubtargetInfo &STI);
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/// If \p Reg is a pseudo reg, return the correct hardware register given
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/// \p STI otherwise return \p Reg.
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unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
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/// \brief Can this operand also contain immediate values?
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bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
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/// \brief Is this floating-point operand?
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bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
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/// \brief Does this opearnd support only inlinable literals?
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bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
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/// \brief Get the size in bits of a register from the register class \p RC.
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unsigned getRegBitWidth(unsigned RCID);
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/// \brief Get the size in bits of a register from the register class \p RC.
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unsigned getRegBitWidth(const MCRegisterClass &RC);
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/// \brief Get size of register operand
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unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
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unsigned OpNo);
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LLVM_READNONE
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inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
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switch (OpInfo.OperandType) {
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case AMDGPU::OPERAND_REG_IMM_INT32:
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case AMDGPU::OPERAND_REG_IMM_FP32:
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case AMDGPU::OPERAND_REG_INLINE_C_INT32:
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case AMDGPU::OPERAND_REG_INLINE_C_FP32:
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return 4;
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case AMDGPU::OPERAND_REG_IMM_INT64:
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case AMDGPU::OPERAND_REG_IMM_FP64:
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case AMDGPU::OPERAND_REG_INLINE_C_INT64:
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case AMDGPU::OPERAND_REG_INLINE_C_FP64:
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return 8;
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case AMDGPU::OPERAND_REG_IMM_INT16:
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case AMDGPU::OPERAND_REG_IMM_FP16:
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case AMDGPU::OPERAND_REG_INLINE_C_INT16:
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case AMDGPU::OPERAND_REG_INLINE_C_FP16:
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return 2;
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default:
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llvm_unreachable("unhandled operand type");
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}
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}
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LLVM_READNONE
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inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
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return getOperandSize(Desc.OpInfo[OpNo]);
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}
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/// \brief Is this literal inlinable
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LLVM_READNONE
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bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
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LLVM_READNONE
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bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
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LLVM_READNONE
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bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
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} // end namespace AMDGPU
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} // end namespace llvm
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#endif
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