forked from OSchip/llvm-project
796 lines
27 KiB
C++
796 lines
27 KiB
C++
//===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonFixupKinds.h"
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#include "MCTargetDesc/HexagonMCCodeEmitter.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "mccodeemitter"
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using namespace llvm;
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using namespace Hexagon;
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
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MCContext &aMCT)
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: MCT(aMCT), MCII(aMII), Addend(new unsigned(0)),
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Extended(new bool(false)), CurrentBundle(new MCInst const *),
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CurrentIndex(new size_t(0)) {}
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uint32_t HexagonMCCodeEmitter::parseBits(size_t Last,
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MCInst const &MCB,
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MCInst const &MCI) const {
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bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
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if (*CurrentIndex == 0) {
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if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
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assert(!Duplex);
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assert(*CurrentIndex != Last);
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return HexagonII::INST_PARSE_LOOP_END;
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}
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}
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if (*CurrentIndex == 1) {
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if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
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assert(!Duplex);
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assert(*CurrentIndex != Last);
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return HexagonII::INST_PARSE_LOOP_END;
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}
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}
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if (Duplex) {
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assert(*CurrentIndex == Last);
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return HexagonII::INST_PARSE_DUPLEX;
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}
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if(*CurrentIndex == Last)
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return HexagonII::INST_PARSE_PACKET_END;
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return HexagonII::INST_PARSE_NOT_END;
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}
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/// EncodeInstruction - Emit the bundle
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void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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MCInst &HMB = const_cast<MCInst &>(MI);
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assert(HexagonMCInstrInfo::isBundle(HMB));
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DEBUG(dbgs() << "Encoding bundle\n";);
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*Addend = 0;
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*Extended = false;
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*CurrentBundle = &MI;
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*CurrentIndex = 0;
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size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
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for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
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MCInst &HMI = const_cast<MCInst &>(*I.getInst());
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verifyInstructionPredicates(HMI,
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computeAvailableFeatures(STI.getFeatureBits()));
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EncodeSingleInstruction(HMI, OS, Fixups, STI,
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parseBits(Last, HMB, HMI));
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*Extended = HexagonMCInstrInfo::isImmext(HMI);
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*Addend += HEXAGON_INSTR_SIZE;
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++*CurrentIndex;
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}
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return;
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}
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static bool RegisterMatches(unsigned Consumer, unsigned Producer,
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unsigned Producer2) {
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if (Consumer == Producer)
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return true;
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if (Consumer == Producer2)
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return true;
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// Calculate if we're a single vector consumer referencing a double producer
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if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
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if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
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return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0);
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return false;
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}
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/// EncodeSingleInstruction - Emit a single
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void HexagonMCCodeEmitter::EncodeSingleInstruction(
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const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI, uint32_t Parse) const {
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assert(!HexagonMCInstrInfo::isBundle(MI));
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uint64_t Binary;
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// Pseudo instructions don't get encoded and shouldn't be here
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// in the first place!
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assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() &&
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"pseudo-instruction found");
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DEBUG(dbgs() << "Encoding insn"
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" `" << HexagonMCInstrInfo::getName(MCII, MI) << "'"
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"\n");
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Binary = getBinaryCodeForInstr(MI, Fixups, STI);
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// Check for unimplemented instructions. Immediate extenders
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// are encoded as zero, so they need to be accounted for.
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if (!Binary &&
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MI.getOpcode() != DuplexIClass0 &&
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MI.getOpcode() != A4_ext) {
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DEBUG(dbgs() << "Unimplemented inst: "
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" `" << HexagonMCInstrInfo::getName(MCII, MI) << "'"
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"\n");
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llvm_unreachable("Unimplemented Instruction");
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}
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Binary |= Parse;
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// if we need to emit a duplexed instruction
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if (MI.getOpcode() >= Hexagon::DuplexIClass0 &&
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MI.getOpcode() <= Hexagon::DuplexIClassF) {
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assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
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"Emitting duplex without duplex parse bits");
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unsigned dupIClass = MI.getOpcode() - Hexagon::DuplexIClass0;
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// 29 is the bit position.
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// 0b1110 =0xE bits are masked off and down shifted by 1 bit.
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// Last bit is moved to bit position 13
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Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13);
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const MCInst *subInst0 = MI.getOperand(0).getInst();
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const MCInst *subInst1 = MI.getOperand(1).getInst();
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// get subinstruction slot 0
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unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI);
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// get subinstruction slot 1
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unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI);
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Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16);
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}
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support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
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++MCNumEmitted;
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}
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namespace {
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void raise_relocation_error(unsigned bits, unsigned kind) {
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std::string Text;
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{
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llvm::raw_string_ostream Stream(Text);
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Stream << "Unrecognized relocation combination bits: " << bits
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<< " kind: " << kind;
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}
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report_fatal_error(Text);
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}
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}
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/// getFixupNoBits - Some insns are not extended and thus have no
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/// bits. These cases require a more brute force method for determining
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/// the correct relocation.
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Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
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MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO,
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const MCSymbolRefExpr::VariantKind kind) const {
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const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
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unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI);
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if (insnType == HexagonII::TypeEXTENDER) {
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switch (kind) {
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case MCSymbolRefExpr::VK_GOTREL:
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return Hexagon::fixup_Hexagon_GOTREL_32_6_X;
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case MCSymbolRefExpr::VK_GOT:
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return Hexagon::fixup_Hexagon_GOT_32_6_X;
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case MCSymbolRefExpr::VK_TPREL:
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return Hexagon::fixup_Hexagon_TPREL_32_6_X;
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case MCSymbolRefExpr::VK_DTPREL:
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return Hexagon::fixup_Hexagon_DTPREL_32_6_X;
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case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
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return Hexagon::fixup_Hexagon_GD_GOT_32_6_X;
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case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
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return Hexagon::fixup_Hexagon_LD_GOT_32_6_X;
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case MCSymbolRefExpr::VK_Hexagon_IE:
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return Hexagon::fixup_Hexagon_IE_32_6_X;
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case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
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return Hexagon::fixup_Hexagon_IE_GOT_32_6_X;
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case MCSymbolRefExpr::VK_Hexagon_PCREL:
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return Hexagon::fixup_Hexagon_B32_PCREL_X;
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case MCSymbolRefExpr::VK_None: {
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auto Insts = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
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for (auto I = Insts.begin(), N = Insts.end(); I != N; ++I) {
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if (I->getInst() == &MI) {
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const MCInst &NextI = *(I+1)->getInst();
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const MCInstrDesc &D = HexagonMCInstrInfo::getDesc(MCII, NextI);
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if (D.isBranch() || D.isCall() ||
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HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR)
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return Hexagon::fixup_Hexagon_B32_PCREL_X;
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return Hexagon::fixup_Hexagon_32_6_X;
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}
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}
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raise_relocation_error(0, kind);
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}
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default:
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raise_relocation_error(0, kind);
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}
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} else if (MCID.isBranch())
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return Hexagon::fixup_Hexagon_B13_PCREL;
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switch (MCID.getOpcode()) {
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case Hexagon::HI:
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case Hexagon::A2_tfrih:
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switch (kind) {
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case MCSymbolRefExpr::VK_GOT:
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return Hexagon::fixup_Hexagon_GOT_HI16;
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case MCSymbolRefExpr::VK_GOTREL:
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return Hexagon::fixup_Hexagon_GOTREL_HI16;
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case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
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return Hexagon::fixup_Hexagon_GD_GOT_HI16;
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case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
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return Hexagon::fixup_Hexagon_LD_GOT_HI16;
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case MCSymbolRefExpr::VK_Hexagon_IE:
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return Hexagon::fixup_Hexagon_IE_HI16;
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case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
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return Hexagon::fixup_Hexagon_IE_GOT_HI16;
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case MCSymbolRefExpr::VK_TPREL:
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return Hexagon::fixup_Hexagon_TPREL_HI16;
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case MCSymbolRefExpr::VK_DTPREL:
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return Hexagon::fixup_Hexagon_DTPREL_HI16;
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case MCSymbolRefExpr::VK_None:
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return Hexagon::fixup_Hexagon_HI16;
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default:
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raise_relocation_error(0, kind);
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}
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case Hexagon::LO:
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case Hexagon::A2_tfril:
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switch (kind) {
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case MCSymbolRefExpr::VK_GOT:
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return Hexagon::fixup_Hexagon_GOT_LO16;
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case MCSymbolRefExpr::VK_GOTREL:
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return Hexagon::fixup_Hexagon_GOTREL_LO16;
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case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
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return Hexagon::fixup_Hexagon_GD_GOT_LO16;
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case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
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return Hexagon::fixup_Hexagon_LD_GOT_LO16;
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case MCSymbolRefExpr::VK_Hexagon_IE:
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return Hexagon::fixup_Hexagon_IE_LO16;
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case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
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return Hexagon::fixup_Hexagon_IE_GOT_LO16;
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case MCSymbolRefExpr::VK_TPREL:
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return Hexagon::fixup_Hexagon_TPREL_LO16;
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case MCSymbolRefExpr::VK_DTPREL:
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return Hexagon::fixup_Hexagon_DTPREL_LO16;
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case MCSymbolRefExpr::VK_None:
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return Hexagon::fixup_Hexagon_LO16;
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default:
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raise_relocation_error(0, kind);
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}
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// The only relocs left should be GP relative:
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default:
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if (MCID.mayStore() || MCID.mayLoad()) {
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for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
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++ImpUses) {
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if (*ImpUses != Hexagon::GP)
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continue;
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switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
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case HexagonII::MemAccessSize::ByteAccess:
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return fixup_Hexagon_GPREL16_0;
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case HexagonII::MemAccessSize::HalfWordAccess:
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return fixup_Hexagon_GPREL16_1;
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case HexagonII::MemAccessSize::WordAccess:
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return fixup_Hexagon_GPREL16_2;
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case HexagonII::MemAccessSize::DoubleWordAccess:
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return fixup_Hexagon_GPREL16_3;
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default:
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raise_relocation_error(0, kind);
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}
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}
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}
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raise_relocation_error(0, kind);
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}
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llvm_unreachable("Relocation exit not taken");
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}
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namespace llvm {
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extern const MCInstrDesc HexagonInsts[];
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}
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namespace {
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bool isPCRel (unsigned Kind) {
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switch(Kind){
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case fixup_Hexagon_B22_PCREL:
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case fixup_Hexagon_B15_PCREL:
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case fixup_Hexagon_B7_PCREL:
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case fixup_Hexagon_B13_PCREL:
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case fixup_Hexagon_B9_PCREL:
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case fixup_Hexagon_B32_PCREL_X:
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case fixup_Hexagon_B22_PCREL_X:
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case fixup_Hexagon_B15_PCREL_X:
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case fixup_Hexagon_B13_PCREL_X:
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case fixup_Hexagon_B9_PCREL_X:
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case fixup_Hexagon_B7_PCREL_X:
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case fixup_Hexagon_32_PCREL:
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case fixup_Hexagon_PLT_B22_PCREL:
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case fixup_Hexagon_GD_PLT_B22_PCREL:
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case fixup_Hexagon_LD_PLT_B22_PCREL:
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case fixup_Hexagon_6_PCREL_X:
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return true;
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default:
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return false;
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}
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}
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}
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unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
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const MCOperand &MO,
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const MCExpr *ME,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const
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{
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if (isa<HexagonMCExpr>(ME))
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ME = &HexagonMCInstrInfo::getExpr(*ME);
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int64_t Value;
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if (ME->evaluateAsAbsolute(Value))
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return Value;
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assert(ME->getKind() == MCExpr::SymbolRef ||
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ME->getKind() == MCExpr::Binary);
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if (ME->getKind() == MCExpr::Binary) {
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MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME);
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getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI);
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getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI);
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return 0;
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}
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Hexagon::Fixups FixupKind =
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Hexagon::Fixups(Hexagon::fixup_Hexagon_TPREL_LO16);
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const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
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const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
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unsigned bits = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
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HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
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const MCSymbolRefExpr::VariantKind kind = MCSRE->getKind();
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DEBUG(dbgs() << "----------------------------------------\n");
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DEBUG(dbgs() << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
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<< "\n");
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DEBUG(dbgs() << "Opcode: " << MCID.getOpcode() << "\n");
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DEBUG(dbgs() << "Relocation bits: " << bits << "\n");
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DEBUG(dbgs() << "Addend: " << *Addend << "\n");
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DEBUG(dbgs() << "----------------------------------------\n");
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switch (bits) {
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default:
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raise_relocation_error(bits, kind);
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case 32:
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switch (kind) {
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case MCSymbolRefExpr::VK_DTPREL:
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FixupKind = *Extended ? Hexagon::fixup_Hexagon_DTPREL_32_6_X
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: Hexagon::fixup_Hexagon_DTPREL_32;
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break;
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case MCSymbolRefExpr::VK_GOT:
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FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOT_32_6_X
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: Hexagon::fixup_Hexagon_GOT_32;
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break;
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case MCSymbolRefExpr::VK_GOTREL:
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FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOTREL_32_6_X
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: Hexagon::fixup_Hexagon_GOTREL_32;
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break;
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case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
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FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_GOT_32_6_X
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: Hexagon::fixup_Hexagon_GD_GOT_32;
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break;
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case MCSymbolRefExpr::VK_Hexagon_IE:
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FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_32_6_X
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: Hexagon::fixup_Hexagon_IE_32;
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break;
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case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
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FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_GOT_32_6_X
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: Hexagon::fixup_Hexagon_IE_GOT_32;
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break;
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case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
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FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_GOT_32_6_X
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: Hexagon::fixup_Hexagon_LD_GOT_32;
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break;
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case MCSymbolRefExpr::VK_Hexagon_PCREL:
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FixupKind = Hexagon::fixup_Hexagon_32_PCREL;
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break;
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case MCSymbolRefExpr::VK_None:
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FixupKind =
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*Extended ? Hexagon::fixup_Hexagon_32_6_X : Hexagon::fixup_Hexagon_32;
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break;
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case MCSymbolRefExpr::VK_TPREL:
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FixupKind = *Extended ? Hexagon::fixup_Hexagon_TPREL_32_6_X
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: Hexagon::fixup_Hexagon_TPREL_32;
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break;
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default:
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raise_relocation_error(bits, kind);
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}
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break;
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case 22:
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switch (kind) {
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case MCSymbolRefExpr::VK_Hexagon_GD_PLT:
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FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL;
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break;
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case MCSymbolRefExpr::VK_Hexagon_LD_PLT:
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FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL;
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break;
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case MCSymbolRefExpr::VK_None:
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FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X
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: Hexagon::fixup_Hexagon_B22_PCREL;
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break;
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case MCSymbolRefExpr::VK_PLT:
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FixupKind = Hexagon::fixup_Hexagon_PLT_B22_PCREL;
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break;
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default:
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raise_relocation_error(bits, kind);
|
|
}
|
|
break;
|
|
|
|
case 16:
|
|
if (*Extended) {
|
|
switch (kind) {
|
|
case MCSymbolRefExpr::VK_DTPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_GOTREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_IE:
|
|
FixupKind = Hexagon::fixup_Hexagon_IE_16_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_None:
|
|
FixupKind = Hexagon::fixup_Hexagon_16_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_TPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X;
|
|
break;
|
|
default:
|
|
raise_relocation_error(bits, kind);
|
|
}
|
|
} else
|
|
switch (kind) {
|
|
case MCSymbolRefExpr::VK_None: {
|
|
if (HexagonMCInstrInfo::s23_2_reloc(*MO.getExpr()))
|
|
FixupKind = Hexagon::fixup_Hexagon_23_REG;
|
|
else
|
|
if (MCID.mayStore() || MCID.mayLoad()) {
|
|
for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
|
|
++ImpUses) {
|
|
if (*ImpUses != Hexagon::GP)
|
|
continue;
|
|
switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
|
|
case HexagonII::MemAccessSize::ByteAccess:
|
|
FixupKind = fixup_Hexagon_GPREL16_0;
|
|
break;
|
|
case HexagonII::MemAccessSize::HalfWordAccess:
|
|
FixupKind = fixup_Hexagon_GPREL16_1;
|
|
break;
|
|
case HexagonII::MemAccessSize::WordAccess:
|
|
FixupKind = fixup_Hexagon_GPREL16_2;
|
|
break;
|
|
case HexagonII::MemAccessSize::DoubleWordAccess:
|
|
FixupKind = fixup_Hexagon_GPREL16_3;
|
|
break;
|
|
default:
|
|
raise_relocation_error(bits, kind);
|
|
}
|
|
}
|
|
} else
|
|
raise_relocation_error(bits, kind);
|
|
break;
|
|
}
|
|
case MCSymbolRefExpr::VK_DTPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_DTPREL_16;
|
|
break;
|
|
case MCSymbolRefExpr::VK_GOTREL:
|
|
if (MCID.getOpcode() == Hexagon::HI)
|
|
FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16;
|
|
else
|
|
FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_GPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_GPREL16_0;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_HI16:
|
|
FixupKind = Hexagon::fixup_Hexagon_HI16;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_LO16:
|
|
FixupKind = Hexagon::fixup_Hexagon_LO16;
|
|
break;
|
|
case MCSymbolRefExpr::VK_TPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_TPREL_16;
|
|
break;
|
|
default:
|
|
raise_relocation_error(bits, kind);
|
|
}
|
|
break;
|
|
|
|
case 15:
|
|
switch (kind) {
|
|
case MCSymbolRefExpr::VK_None:
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_B15_PCREL_X
|
|
: Hexagon::fixup_Hexagon_B15_PCREL;
|
|
break;
|
|
default:
|
|
raise_relocation_error(bits, kind);
|
|
}
|
|
break;
|
|
|
|
case 13:
|
|
switch (kind) {
|
|
case MCSymbolRefExpr::VK_None:
|
|
FixupKind = Hexagon::fixup_Hexagon_B13_PCREL;
|
|
break;
|
|
default:
|
|
raise_relocation_error(bits, kind);
|
|
}
|
|
break;
|
|
|
|
case 12:
|
|
if (*Extended)
|
|
switch (kind) {
|
|
// There isn't a GOT_12_X, both 11_X and 16_X resolve to 6/26
|
|
case MCSymbolRefExpr::VK_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_GOTREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_None:
|
|
FixupKind = Hexagon::fixup_Hexagon_12_X;
|
|
break;
|
|
default:
|
|
raise_relocation_error(bits, kind);
|
|
}
|
|
else
|
|
raise_relocation_error(bits, kind);
|
|
break;
|
|
|
|
case 11:
|
|
if (*Extended)
|
|
switch (kind) {
|
|
case MCSymbolRefExpr::VK_DTPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_DTPREL_11_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_GOTREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GD_GOT_11_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_IE_GOT_11_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_LD_GOT_11_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_None:
|
|
FixupKind = Hexagon::fixup_Hexagon_11_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_TPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X;
|
|
break;
|
|
default:
|
|
raise_relocation_error(bits, kind);
|
|
}
|
|
else {
|
|
switch (kind) {
|
|
case MCSymbolRefExpr::VK_TPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X;
|
|
break;
|
|
default:
|
|
raise_relocation_error(bits, kind);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 10:
|
|
if (*Extended) {
|
|
switch (kind) {
|
|
case MCSymbolRefExpr::VK_None:
|
|
FixupKind = Hexagon::fixup_Hexagon_10_X;
|
|
break;
|
|
default:
|
|
raise_relocation_error(bits, kind);
|
|
}
|
|
} else
|
|
raise_relocation_error(bits, kind);
|
|
break;
|
|
|
|
case 9:
|
|
if (MCID.isBranch() ||
|
|
(HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
|
|
: Hexagon::fixup_Hexagon_B9_PCREL;
|
|
else if (*Extended)
|
|
FixupKind = Hexagon::fixup_Hexagon_9_X;
|
|
else
|
|
raise_relocation_error(bits, kind);
|
|
break;
|
|
|
|
case 8:
|
|
if (*Extended)
|
|
FixupKind = Hexagon::fixup_Hexagon_8_X;
|
|
else
|
|
raise_relocation_error(bits, kind);
|
|
break;
|
|
|
|
case 7:
|
|
if (MCID.isBranch() ||
|
|
(HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
|
|
FixupKind = *Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
|
|
: Hexagon::fixup_Hexagon_B7_PCREL;
|
|
else if (*Extended)
|
|
FixupKind = Hexagon::fixup_Hexagon_7_X;
|
|
else
|
|
raise_relocation_error(bits, kind);
|
|
break;
|
|
|
|
case 6:
|
|
if (*Extended) {
|
|
switch (kind) {
|
|
case MCSymbolRefExpr::VK_DTPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X;
|
|
break;
|
|
// This is part of an extender, GOT_11 is a
|
|
// Word32_U6 unsigned/truncated reloc.
|
|
case MCSymbolRefExpr::VK_GOT:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_GOTREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Hexagon_PCREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_6_PCREL_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_TPREL:
|
|
FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X;
|
|
break;
|
|
case MCSymbolRefExpr::VK_None:
|
|
FixupKind = Hexagon::fixup_Hexagon_6_X;
|
|
break;
|
|
default:
|
|
raise_relocation_error(bits, kind);
|
|
}
|
|
} else
|
|
raise_relocation_error(bits, kind);
|
|
break;
|
|
|
|
case 0:
|
|
FixupKind = getFixupNoBits(MCII, MI, MO, kind);
|
|
break;
|
|
}
|
|
|
|
MCExpr const *FixupExpression =
|
|
(*Addend > 0 && isPCRel(FixupKind))
|
|
? MCBinaryExpr::createAdd(MO.getExpr(),
|
|
MCConstantExpr::create(*Addend, MCT), MCT)
|
|
: MO.getExpr();
|
|
|
|
MCFixup fixup = MCFixup::create(*Addend, FixupExpression,
|
|
MCFixupKind(FixupKind), MI.getLoc());
|
|
Fixups.push_back(fixup);
|
|
// All of the information is in the fixup.
|
|
return 0;
|
|
}
|
|
|
|
unsigned
|
|
HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
MCSubtargetInfo const &STI) const {
|
|
size_t OperandNumber = ~0U;
|
|
for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i)
|
|
if (&MI.getOperand(i) == &MO) {
|
|
OperandNumber = i;
|
|
break;
|
|
}
|
|
assert((OperandNumber != ~0U) && "Operand not found");
|
|
|
|
if (HexagonMCInstrInfo::isNewValue(MCII, MI) &&
|
|
&MO == &MI.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, MI))) {
|
|
// Calculate the new value distance to the associated producer
|
|
MCOperand const &MCO =
|
|
MI.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, MI));
|
|
unsigned SOffset = 0;
|
|
unsigned VOffset = 0;
|
|
unsigned Register = MCO.getReg();
|
|
unsigned Register1;
|
|
unsigned Register2;
|
|
auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
|
|
auto i = Instructions.begin() + *CurrentIndex - 1;
|
|
for (;; --i) {
|
|
assert(i != Instructions.begin() - 1 && "Couldn't find producer");
|
|
MCInst const &Inst = *i->getInst();
|
|
if (HexagonMCInstrInfo::isImmext(Inst))
|
|
continue;
|
|
++SOffset;
|
|
if (HexagonMCInstrInfo::isVector(MCII, Inst))
|
|
// Vector instructions don't count scalars
|
|
++VOffset;
|
|
Register1 =
|
|
HexagonMCInstrInfo::hasNewValue(MCII, Inst)
|
|
? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg()
|
|
: static_cast<unsigned>(Hexagon::NoRegister);
|
|
Register2 =
|
|
HexagonMCInstrInfo::hasNewValue2(MCII, Inst)
|
|
? HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg()
|
|
: static_cast<unsigned>(Hexagon::NoRegister);
|
|
if (!RegisterMatches(Register, Register1, Register2))
|
|
// This isn't the register we're looking for
|
|
continue;
|
|
if (!HexagonMCInstrInfo::isPredicated(MCII, Inst))
|
|
// Producer is unpredicated
|
|
break;
|
|
assert(HexagonMCInstrInfo::isPredicated(MCII, MI) &&
|
|
"Unpredicated consumer depending on predicated producer");
|
|
if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
|
|
HexagonMCInstrInfo::isPredicatedTrue(MCII, MI))
|
|
// Producer predicate sense matched ours
|
|
break;
|
|
}
|
|
// Hexagon PRM 10.11 Construct Nt from distance
|
|
unsigned Offset =
|
|
HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset : SOffset;
|
|
Offset <<= 1;
|
|
Offset |=
|
|
HexagonMCInstrInfo::SubregisterBit(Register, Register1, Register2);
|
|
return Offset;
|
|
}
|
|
assert(!MO.isImm());
|
|
if (MO.isReg()) {
|
|
unsigned Reg = MO.getReg();
|
|
if (HexagonMCInstrInfo::isSubInstruction(MI) ||
|
|
llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCJ)
|
|
return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg);
|
|
switch(MI.getOpcode()){
|
|
case Hexagon::A2_tfrrcr:
|
|
case Hexagon::A2_tfrcrr:
|
|
if(Reg == Hexagon::M0)
|
|
Reg = Hexagon::C6;
|
|
if(Reg == Hexagon::M1)
|
|
Reg = Hexagon::C7;
|
|
}
|
|
return MCT.getRegisterInfo()->getEncodingValue(Reg);
|
|
}
|
|
|
|
return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
|
|
}
|
|
|
|
MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
|
|
MCRegisterInfo const &MRI,
|
|
MCContext &MCT) {
|
|
return new HexagonMCCodeEmitter(MII, MCT);
|
|
}
|
|
|
|
#define ENABLE_INSTR_PREDICATE_VERIFIER
|
|
#include "HexagonGenMCCodeEmitter.inc"
|