forked from OSchip/llvm-project
199 lines
6.3 KiB
C++
199 lines
6.3 KiB
C++
//===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an Hexagon MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "HexagonInstPrinter.h"
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#include "Hexagon.h"
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#include "HexagonAsmPrinter.h"
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#include "HexagonMCInst.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cstdio>
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using namespace llvm;
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#define GET_INSTRUCTION_NAME
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#include "HexagonGenAsmWriter.inc"
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StringRef HexagonInstPrinter::getOpcodeName(unsigned Opcode) const {
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return MII.getName(Opcode);
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}
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StringRef HexagonInstPrinter::getRegName(unsigned RegNo) const {
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return getRegisterName(RegNo);
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}
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void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot) {
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printInst((const HexagonMCInst*)(MI), O, Annot);
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}
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void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream &O,
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StringRef Annot) {
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const char packetPadding[] = " ";
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const char startPacket = '{',
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endPacket = '}';
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// TODO: add outer HW loop when it's supported too.
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if (MI->getOpcode() == Hexagon::ENDLOOP0) {
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// Ending a harware loop is different from ending an regular packet.
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assert(MI->isEndPacket() && "Loop end must also end the packet");
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if (MI->isStartPacket()) {
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// There must be a packet to end a loop.
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// FIXME: when shuffling is always run, this shouldn't be needed.
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HexagonMCInst Nop;
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StringRef NoAnnot;
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Nop.setOpcode (Hexagon::NOP);
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Nop.setStartPacket (MI->isStartPacket());
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printInst (&Nop, O, NoAnnot);
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}
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// Close the packet.
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if (MI->isEndPacket())
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O << packetPadding << endPacket;
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printInstruction(MI, O);
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}
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else {
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// Prefix the insn opening the packet.
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if (MI->isStartPacket())
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O << packetPadding << startPacket << '\n';
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printInstruction(MI, O);
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// Suffix the insn closing the packet.
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if (MI->isEndPacket())
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// Suffix the packet in a new line always, since the GNU assembler has
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// issues with a closing brace on the same line as CONST{32,64}.
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O << '\n' << packetPadding << endPacket;
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}
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printAnnotation(O, Annot);
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}
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void HexagonInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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const MCOperand& MO = MI->getOperand(OpNo);
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if (MO.isReg()) {
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O << getRegisterName(MO.getReg());
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} else if(MO.isExpr()) {
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O << *MO.getExpr();
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} else if(MO.isImm()) {
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printImmOperand(MI, OpNo, O);
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} else {
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llvm_unreachable("Unknown operand");
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}
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}
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void HexagonInstPrinter::printImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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O << MI->getOperand(OpNo).getImm();
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}
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void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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O << MI->getOperand(OpNo).getImm();
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}
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void HexagonInstPrinter::printUnsignedImmOperand(const MCInst *MI,
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unsigned OpNo, raw_ostream &O) const {
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O << MI->getOperand(OpNo).getImm();
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}
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void HexagonInstPrinter::printNegImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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O << -MI->getOperand(OpNo).getImm();
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}
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void HexagonInstPrinter::printNOneImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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O << -1;
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}
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void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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const MCOperand& MO0 = MI->getOperand(OpNo);
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const MCOperand& MO1 = MI->getOperand(OpNo + 1);
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O << getRegisterName(MO0.getReg());
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O << " + #" << MO1.getImm();
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}
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void HexagonInstPrinter::printFrameIndexOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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const MCOperand& MO0 = MI->getOperand(OpNo);
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const MCOperand& MO1 = MI->getOperand(OpNo + 1);
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O << getRegisterName(MO0.getReg()) << ", #" << MO1.getImm();
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}
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void HexagonInstPrinter::printGlobalOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
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printOperand(MI, OpNo, O);
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}
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void HexagonInstPrinter::printJumpTable(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
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printOperand(MI, OpNo, O);
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}
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void HexagonInstPrinter::printConstantPool(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
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printOperand(MI, OpNo, O);
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}
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void HexagonInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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// Branches can take an immediate operand. This is used by the branch
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// selection pass to print $+8, an eight byte displacement from the PC.
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assert("Unknown branch operand.");
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}
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void HexagonInstPrinter::printCallOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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}
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void HexagonInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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}
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void HexagonInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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}
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void HexagonInstPrinter::printSymbol(const MCInst *MI, unsigned OpNo,
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raw_ostream &O, bool hi) const {
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const MCOperand& MO = MI->getOperand(OpNo);
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O << '#' << (hi? "HI": "LO") << '(';
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if (MO.isImm()) {
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O << '#';
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printOperand(MI, OpNo, O);
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} else {
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assert("Unknown symbol operand");
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printOperand(MI, OpNo, O);
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}
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O << ')';
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}
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