llvm-project/llvm/include
Hsiangkai Wang 66a49aef69 [RISCV] Implement vsoxseg/vsuxseg intrinsics.
Define vsoxseg/vsuxseg intrinsics and pseudo instructions.
Lower vsoxseg/vsuxseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.

Differential Revision: https://reviews.llvm.org/D94940
2021-01-23 08:54:56 +08:00
..
llvm [RISCV] Implement vsoxseg/vsuxseg intrinsics. 2021-01-23 08:54:56 +08:00
llvm-c [X86] Add x86_amx type for intel AMX. 2020-12-30 13:52:13 +08:00