llvm-project/llvm/test/CodeGen
Matt Arsenault 62b1737081 R600: Add mul24 intrinsics
llvm-svn: 208604
2014-05-12 17:49:57 +00:00
..
AArch64 AArch64/ARM64: optimise vector selects & enable test 2014-05-07 14:10:27 +00:00
ARM ARM: Implement big endian bit-conversion for NEON type 2014-05-12 11:19:20 +00:00
ARM64 ARM64: fix SELECT_CC lowering in absence of NaNs. 2014-05-10 07:37:50 +00:00
CPP Begin adding docs and IR-level support for the inalloca attribute 2013-12-19 02:14:12 +00:00
Generic MC: move test from Generic to COFF 2014-04-23 21:41:07 +00:00
Hexagon Fix broken CHECK lines 2014-02-16 07:31:05 +00:00
Inputs Debug Info: update testing cases to specify the debug info version number. 2013-11-22 21:49:45 +00:00
MSP430 Mark FPB as a reserved register when needed. 2014-04-02 13:13:56 +00:00
Mips Allow sret on the second parameter as well as the first 2014-05-09 22:32:13 +00:00
NVPTX Fix the test: DCE optimized away everything. 2014-04-21 17:23:12 +00:00
PowerPC [PowerPC] Add global named register support 2014-05-11 19:29:11 +00:00
R600 R600: Add mul24 intrinsics 2014-05-12 17:49:57 +00:00
SPARC Allow sret on the second parameter as well as the first 2014-05-09 22:32:13 +00:00
SystemZ Reenable use of TBAA during CodeGen 2014-04-12 01:26:00 +00:00
Thumb Make this test not match its own filename, when being run from a path that includes the string 'add'. 2014-04-15 22:29:32 +00:00
Thumb2 Move the segmented stack switch to a function attribute 2014-04-10 22:58:43 +00:00
X86 X86: Make sure that we have SSE4.1 before we generate insertps nodes. 2014-05-12 13:12:08 +00:00
XCore Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl" 2014-04-21 17:57:07 +00:00