llvm-project/llvm/lib/Target/RISCV/AsmParser
Hsiangkai Wang a2d19bad07 [RISCV] Use whole register load/store for generic load/store.
In vector v0.10, there are whole vector register load/store
instructions. I suggest to use the whole register load/store
instructions for generic load/store for scalable vector types. It could
save up vset{i}vl{i} for these load/store.

For fractional LMUL, I keep to use vle{eew}.v/vse{eew}.v instructions to
load/store partial vector registers.

Differential Revision: https://reviews.llvm.org/D95853
2021-02-09 15:52:04 +08:00
..
CMakeLists.txt [RISCV] Merge Utils library into MCTargetDesc 2021-01-14 11:47:30 -08:00
RISCVAsmParser.cpp [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00