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llvm-project/mlir/lib/Conversion
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Matthias Springer 95f8135043 [mlir] Change vector.transfer_read/write "masked" attribute to "in_bounds". 
This is in preparation for adding a new "mask" operand. The existing "masked" attribute was used to specify dimensions that may be out-of-bounds. Such transfers can be lowered to masked load/stores. The new "in_bounds" attribute is used to specify dimensions that are guaranteed to be within bounds. (Semantics is inverted.)

Differential Revision: https://reviews.llvm.org/D99639
 		2021-03-31 18:04:22 +09:00
..
AffineToStandard [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
ArmSVEToLLVM [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
AsyncToLLVM Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
ComplexToLLVM [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
GPUCommon Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
GPUToNVVM [mlir] introduce data layout entry for index type 2021-03-24 15:13:42 +01:00
GPUToROCDL [mlir] introduce data layout entry for index type 2021-03-24 15:13:42 +01:00
GPUToSPIRV [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
GPUToVulkan Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
LinalgToLLVM Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
LinalgToSPIRV Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
LinalgToStandard Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
OpenMPToLLVM [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
PDLToPDLInterp [mlir][pdl] Cast the OperationPosition to Position to fix MSVC miscompile 2021-03-16 16:11:14 -07:00
SCFToGPU [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
SCFToOpenMP Rename FrozenRewritePatternList -> FrozenRewritePatternSet; NFC. 2021-03-22 17:40:45 -07:00
SCFToSPIRV [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
SCFToStandard [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
SPIRVToLLVM Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
ShapeToStandard Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
StandardToLLVM [mlir] introduce data layout entry for index type 2021-03-24 15:13:42 +01:00
StandardToSPIRV [mlir] Change vector.transfer_read/write "masked" attribute to "in_bounds". 2021-03-31 18:04:22 +09:00
TosaToLinalg [mlir][tosa] Add tosa.bitwise_not lowering to constant and xor 2021-03-24 17:27:27 -07:00
TosaToSCF [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
TosaToStandard [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
VectorToLLVM [mlir] Change vector.transfer_read/write "masked" attribute to "in_bounds". 2021-03-31 18:04:22 +09:00
VectorToROCDL [mlir] Change vector.transfer_read/write "masked" attribute to "in_bounds". 2021-03-31 18:04:22 +09:00
VectorToSCF [mlir] Change vector.transfer_read/write "masked" attribute to "in_bounds". 2021-03-31 18:04:22 +09:00
VectorToSPIRV Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
CMakeLists.txt [mlir] squash LLVM_AVX512 dialect into AVX512 2021-03-10 13:07:26 +01:00
PassDetail.h [mlir][amx] Add Intel AMX dialect (architectural-specific vector dialect) 2021-03-15 17:59:05 -07:00