forked from OSchip/llvm-project
582 lines
20 KiB
C++
582 lines
20 KiB
C++
//===- VPlan.cpp - Vectorizer Plan ----------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This is the LLVM vectorization plan. It represents a candidate for
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/// vectorization, allowing to plan and optimize how to vectorize a given loop
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/// before generating LLVM-IR.
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/// The vectorizer uses vectorization plans to estimate the costs of potential
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/// candidates and if profitable to execute the desired plan, generating vector
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/// LLVM-IR code.
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///
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//===----------------------------------------------------------------------===//
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#include "VPlan.h"
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#include "VPlanDominatorTree.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/CFG.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/GenericDomTreeConstruction.h"
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#include "llvm/Support/GraphWriter.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Transforms/Utils/BasicBlockUtils.h"
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#include <cassert>
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#include <iterator>
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#include <string>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "vplan"
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raw_ostream &llvm::operator<<(raw_ostream &OS, const VPValue &V) {
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if (const VPInstruction *Instr = dyn_cast<VPInstruction>(&V))
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Instr->print(OS);
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else
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V.printAsOperand(OS);
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return OS;
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}
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/// \return the VPBasicBlock that is the entry of Block, possibly indirectly.
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const VPBasicBlock *VPBlockBase::getEntryBasicBlock() const {
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const VPBlockBase *Block = this;
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while (const VPRegionBlock *Region = dyn_cast<VPRegionBlock>(Block))
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Block = Region->getEntry();
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return cast<VPBasicBlock>(Block);
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}
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VPBasicBlock *VPBlockBase::getEntryBasicBlock() {
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VPBlockBase *Block = this;
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while (VPRegionBlock *Region = dyn_cast<VPRegionBlock>(Block))
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Block = Region->getEntry();
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return cast<VPBasicBlock>(Block);
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}
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/// \return the VPBasicBlock that is the exit of Block, possibly indirectly.
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const VPBasicBlock *VPBlockBase::getExitBasicBlock() const {
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const VPBlockBase *Block = this;
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while (const VPRegionBlock *Region = dyn_cast<VPRegionBlock>(Block))
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Block = Region->getExit();
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return cast<VPBasicBlock>(Block);
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}
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VPBasicBlock *VPBlockBase::getExitBasicBlock() {
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VPBlockBase *Block = this;
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while (VPRegionBlock *Region = dyn_cast<VPRegionBlock>(Block))
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Block = Region->getExit();
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return cast<VPBasicBlock>(Block);
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}
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VPBlockBase *VPBlockBase::getEnclosingBlockWithSuccessors() {
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if (!Successors.empty() || !Parent)
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return this;
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assert(Parent->getExit() == this &&
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"Block w/o successors not the exit of its parent.");
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return Parent->getEnclosingBlockWithSuccessors();
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}
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VPBlockBase *VPBlockBase::getEnclosingBlockWithPredecessors() {
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if (!Predecessors.empty() || !Parent)
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return this;
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assert(Parent->getEntry() == this &&
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"Block w/o predecessors not the entry of its parent.");
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return Parent->getEnclosingBlockWithPredecessors();
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}
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void VPBlockBase::deleteCFG(VPBlockBase *Entry) {
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SmallVector<VPBlockBase *, 8> Blocks;
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for (VPBlockBase *Block : depth_first(Entry))
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Blocks.push_back(Block);
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for (VPBlockBase *Block : Blocks)
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delete Block;
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}
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BasicBlock *
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VPBasicBlock::createEmptyBasicBlock(VPTransformState::CFGState &CFG) {
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// BB stands for IR BasicBlocks. VPBB stands for VPlan VPBasicBlocks.
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// Pred stands for Predessor. Prev stands for Previous - last visited/created.
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BasicBlock *PrevBB = CFG.PrevBB;
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BasicBlock *NewBB = BasicBlock::Create(PrevBB->getContext(), getName(),
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PrevBB->getParent(), CFG.LastBB);
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LLVM_DEBUG(dbgs() << "LV: created " << NewBB->getName() << '\n');
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// Hook up the new basic block to its predecessors.
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for (VPBlockBase *PredVPBlock : getHierarchicalPredecessors()) {
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VPBasicBlock *PredVPBB = PredVPBlock->getExitBasicBlock();
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auto &PredVPSuccessors = PredVPBB->getSuccessors();
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BasicBlock *PredBB = CFG.VPBB2IRBB[PredVPBB];
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assert(PredBB && "Predecessor basic-block not found building successor.");
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auto *PredBBTerminator = PredBB->getTerminator();
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LLVM_DEBUG(dbgs() << "LV: draw edge from" << PredBB->getName() << '\n');
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if (isa<UnreachableInst>(PredBBTerminator)) {
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assert(PredVPSuccessors.size() == 1 &&
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"Predecessor ending w/o branch must have single successor.");
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PredBBTerminator->eraseFromParent();
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BranchInst::Create(NewBB, PredBB);
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} else {
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assert(PredVPSuccessors.size() == 2 &&
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"Predecessor ending with branch must have two successors.");
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unsigned idx = PredVPSuccessors.front() == this ? 0 : 1;
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assert(!PredBBTerminator->getSuccessor(idx) &&
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"Trying to reset an existing successor block.");
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PredBBTerminator->setSuccessor(idx, NewBB);
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}
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}
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return NewBB;
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}
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void VPBasicBlock::execute(VPTransformState *State) {
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bool Replica = State->Instance &&
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!(State->Instance->Part == 0 && State->Instance->Lane == 0);
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VPBasicBlock *PrevVPBB = State->CFG.PrevVPBB;
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VPBlockBase *SingleHPred = nullptr;
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BasicBlock *NewBB = State->CFG.PrevBB; // Reuse it if possible.
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// 1. Create an IR basic block, or reuse the last one if possible.
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// The last IR basic block is reused, as an optimization, in three cases:
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// A. the first VPBB reuses the loop header BB - when PrevVPBB is null;
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// B. when the current VPBB has a single (hierarchical) predecessor which
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// is PrevVPBB and the latter has a single (hierarchical) successor; and
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// C. when the current VPBB is an entry of a region replica - where PrevVPBB
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// is the exit of this region from a previous instance, or the predecessor
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// of this region.
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if (PrevVPBB && /* A */
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!((SingleHPred = getSingleHierarchicalPredecessor()) &&
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SingleHPred->getExitBasicBlock() == PrevVPBB &&
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PrevVPBB->getSingleHierarchicalSuccessor()) && /* B */
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!(Replica && getPredecessors().empty())) { /* C */
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NewBB = createEmptyBasicBlock(State->CFG);
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State->Builder.SetInsertPoint(NewBB);
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// Temporarily terminate with unreachable until CFG is rewired.
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UnreachableInst *Terminator = State->Builder.CreateUnreachable();
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State->Builder.SetInsertPoint(Terminator);
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// Register NewBB in its loop. In innermost loops its the same for all BB's.
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Loop *L = State->LI->getLoopFor(State->CFG.LastBB);
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L->addBasicBlockToLoop(NewBB, *State->LI);
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State->CFG.PrevBB = NewBB;
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}
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// 2. Fill the IR basic block with IR instructions.
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LLVM_DEBUG(dbgs() << "LV: vectorizing VPBB:" << getName()
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<< " in BB:" << NewBB->getName() << '\n');
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State->CFG.VPBB2IRBB[this] = NewBB;
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State->CFG.PrevVPBB = this;
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for (VPRecipeBase &Recipe : Recipes)
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Recipe.execute(*State);
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LLVM_DEBUG(dbgs() << "LV: filled BB:" << *NewBB);
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}
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void VPRegionBlock::execute(VPTransformState *State) {
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ReversePostOrderTraversal<VPBlockBase *> RPOT(Entry);
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if (!isReplicator()) {
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// Visit the VPBlocks connected to "this", starting from it.
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for (VPBlockBase *Block : RPOT) {
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LLVM_DEBUG(dbgs() << "LV: VPBlock in RPO " << Block->getName() << '\n');
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Block->execute(State);
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}
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return;
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}
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assert(!State->Instance && "Replicating a Region with non-null instance.");
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// Enter replicating mode.
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State->Instance = {0, 0};
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for (unsigned Part = 0, UF = State->UF; Part < UF; ++Part) {
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State->Instance->Part = Part;
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for (unsigned Lane = 0, VF = State->VF; Lane < VF; ++Lane) {
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State->Instance->Lane = Lane;
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// Visit the VPBlocks connected to \p this, starting from it.
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for (VPBlockBase *Block : RPOT) {
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LLVM_DEBUG(dbgs() << "LV: VPBlock in RPO " << Block->getName() << '\n');
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Block->execute(State);
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}
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}
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}
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// Exit replicating mode.
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State->Instance.reset();
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}
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void VPRecipeBase::insertBefore(VPRecipeBase *InsertPos) {
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Parent = InsertPos->getParent();
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Parent->getRecipeList().insert(InsertPos->getIterator(), this);
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}
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iplist<VPRecipeBase>::iterator VPRecipeBase::eraseFromParent() {
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return getParent()->getRecipeList().erase(getIterator());
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}
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void VPInstruction::generateInstruction(VPTransformState &State,
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unsigned Part) {
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IRBuilder<> &Builder = State.Builder;
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if (Instruction::isBinaryOp(getOpcode())) {
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Value *A = State.get(getOperand(0), Part);
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Value *B = State.get(getOperand(1), Part);
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Value *V = Builder.CreateBinOp((Instruction::BinaryOps)getOpcode(), A, B);
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State.set(this, V, Part);
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return;
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}
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switch (getOpcode()) {
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case VPInstruction::Not: {
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Value *A = State.get(getOperand(0), Part);
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Value *V = Builder.CreateNot(A);
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State.set(this, V, Part);
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break;
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}
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default:
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llvm_unreachable("Unsupported opcode for instruction");
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}
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}
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void VPInstruction::execute(VPTransformState &State) {
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assert(!State.Instance && "VPInstruction executing an Instance");
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for (unsigned Part = 0; Part < State.UF; ++Part)
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generateInstruction(State, Part);
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}
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void VPInstruction::print(raw_ostream &O, const Twine &Indent) const {
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O << " +\n" << Indent << "\"EMIT ";
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print(O);
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O << "\\l\"";
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}
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void VPInstruction::print(raw_ostream &O) const {
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printAsOperand(O);
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O << " = ";
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switch (getOpcode()) {
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case VPInstruction::Not:
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O << "not";
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break;
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default:
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O << Instruction::getOpcodeName(getOpcode());
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}
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for (const VPValue *Operand : operands()) {
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O << " ";
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Operand->printAsOperand(O);
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}
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}
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/// Generate the code inside the body of the vectorized loop. Assumes a single
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/// LoopVectorBody basic-block was created for this. Introduce additional
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/// basic-blocks as needed, and fill them all.
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void VPlan::execute(VPTransformState *State) {
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// 0. Set the reverse mapping from VPValues to Values for code generation.
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for (auto &Entry : Value2VPValue)
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State->VPValue2Value[Entry.second] = Entry.first;
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BasicBlock *VectorPreHeaderBB = State->CFG.PrevBB;
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BasicBlock *VectorHeaderBB = VectorPreHeaderBB->getSingleSuccessor();
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assert(VectorHeaderBB && "Loop preheader does not have a single successor.");
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BasicBlock *VectorLatchBB = VectorHeaderBB;
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// 1. Make room to generate basic-blocks inside loop body if needed.
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VectorLatchBB = VectorHeaderBB->splitBasicBlock(
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VectorHeaderBB->getFirstInsertionPt(), "vector.body.latch");
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Loop *L = State->LI->getLoopFor(VectorHeaderBB);
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L->addBasicBlockToLoop(VectorLatchBB, *State->LI);
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// Remove the edge between Header and Latch to allow other connections.
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// Temporarily terminate with unreachable until CFG is rewired.
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// Note: this asserts the generated code's assumption that
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// getFirstInsertionPt() can be dereferenced into an Instruction.
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VectorHeaderBB->getTerminator()->eraseFromParent();
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State->Builder.SetInsertPoint(VectorHeaderBB);
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UnreachableInst *Terminator = State->Builder.CreateUnreachable();
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State->Builder.SetInsertPoint(Terminator);
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// 2. Generate code in loop body.
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State->CFG.PrevVPBB = nullptr;
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State->CFG.PrevBB = VectorHeaderBB;
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State->CFG.LastBB = VectorLatchBB;
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for (VPBlockBase *Block : depth_first(Entry))
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Block->execute(State);
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// 3. Merge the temporary latch created with the last basic-block filled.
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BasicBlock *LastBB = State->CFG.PrevBB;
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// Connect LastBB to VectorLatchBB to facilitate their merge.
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assert(isa<UnreachableInst>(LastBB->getTerminator()) &&
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"Expected VPlan CFG to terminate with unreachable");
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LastBB->getTerminator()->eraseFromParent();
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BranchInst::Create(VectorLatchBB, LastBB);
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// Merge LastBB with Latch.
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bool Merged = MergeBlockIntoPredecessor(VectorLatchBB, nullptr, State->LI);
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(void)Merged;
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assert(Merged && "Could not merge last basic block with latch.");
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VectorLatchBB = LastBB;
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updateDominatorTree(State->DT, VectorPreHeaderBB, VectorLatchBB);
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}
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void VPlan::updateDominatorTree(DominatorTree *DT, BasicBlock *LoopPreHeaderBB,
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BasicBlock *LoopLatchBB) {
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BasicBlock *LoopHeaderBB = LoopPreHeaderBB->getSingleSuccessor();
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assert(LoopHeaderBB && "Loop preheader does not have a single successor.");
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DT->addNewBlock(LoopHeaderBB, LoopPreHeaderBB);
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// The vector body may be more than a single basic-block by this point.
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// Update the dominator tree information inside the vector body by propagating
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// it from header to latch, expecting only triangular control-flow, if any.
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BasicBlock *PostDomSucc = nullptr;
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for (auto *BB = LoopHeaderBB; BB != LoopLatchBB; BB = PostDomSucc) {
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// Get the list of successors of this block.
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std::vector<BasicBlock *> Succs(succ_begin(BB), succ_end(BB));
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assert(Succs.size() <= 2 &&
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"Basic block in vector loop has more than 2 successors.");
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PostDomSucc = Succs[0];
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if (Succs.size() == 1) {
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assert(PostDomSucc->getSinglePredecessor() &&
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"PostDom successor has more than one predecessor.");
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DT->addNewBlock(PostDomSucc, BB);
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continue;
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}
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BasicBlock *InterimSucc = Succs[1];
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if (PostDomSucc->getSingleSuccessor() == InterimSucc) {
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PostDomSucc = Succs[1];
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InterimSucc = Succs[0];
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}
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assert(InterimSucc->getSingleSuccessor() == PostDomSucc &&
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"One successor of a basic block does not lead to the other.");
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assert(InterimSucc->getSinglePredecessor() &&
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"Interim successor has more than one predecessor.");
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assert(pred_size(PostDomSucc) == 2 &&
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"PostDom successor has more than two predecessors.");
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DT->addNewBlock(InterimSucc, BB);
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DT->addNewBlock(PostDomSucc, BB);
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}
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}
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const Twine VPlanPrinter::getUID(const VPBlockBase *Block) {
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return (isa<VPRegionBlock>(Block) ? "cluster_N" : "N") +
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Twine(getOrCreateBID(Block));
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}
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const Twine VPlanPrinter::getOrCreateName(const VPBlockBase *Block) {
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const std::string &Name = Block->getName();
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if (!Name.empty())
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return Name;
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return "VPB" + Twine(getOrCreateBID(Block));
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}
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void VPlanPrinter::dump() {
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Depth = 1;
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bumpIndent(0);
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OS << "digraph VPlan {\n";
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OS << "graph [labelloc=t, fontsize=30; label=\"Vectorization Plan";
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if (!Plan.getName().empty())
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OS << "\\n" << DOT::EscapeString(Plan.getName());
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if (!Plan.Value2VPValue.empty()) {
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OS << ", where:";
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for (auto Entry : Plan.Value2VPValue) {
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OS << "\\n" << *Entry.second;
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OS << DOT::EscapeString(" := ");
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Entry.first->printAsOperand(OS, false);
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}
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}
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OS << "\"]\n";
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OS << "node [shape=rect, fontname=Courier, fontsize=30]\n";
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OS << "edge [fontname=Courier, fontsize=30]\n";
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OS << "compound=true\n";
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for (VPBlockBase *Block : depth_first(Plan.getEntry()))
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dumpBlock(Block);
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OS << "}\n";
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}
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void VPlanPrinter::dumpBlock(const VPBlockBase *Block) {
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if (const VPBasicBlock *BasicBlock = dyn_cast<VPBasicBlock>(Block))
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dumpBasicBlock(BasicBlock);
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else if (const VPRegionBlock *Region = dyn_cast<VPRegionBlock>(Block))
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dumpRegion(Region);
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else
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llvm_unreachable("Unsupported kind of VPBlock.");
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}
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void VPlanPrinter::drawEdge(const VPBlockBase *From, const VPBlockBase *To,
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bool Hidden, const Twine &Label) {
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// Due to "dot" we print an edge between two regions as an edge between the
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// exit basic block and the entry basic of the respective regions.
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const VPBlockBase *Tail = From->getExitBasicBlock();
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const VPBlockBase *Head = To->getEntryBasicBlock();
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OS << Indent << getUID(Tail) << " -> " << getUID(Head);
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OS << " [ label=\"" << Label << '\"';
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if (Tail != From)
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OS << " ltail=" << getUID(From);
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if (Head != To)
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OS << " lhead=" << getUID(To);
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if (Hidden)
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OS << "; splines=none";
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OS << "]\n";
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}
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void VPlanPrinter::dumpEdges(const VPBlockBase *Block) {
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auto &Successors = Block->getSuccessors();
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if (Successors.size() == 1)
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drawEdge(Block, Successors.front(), false, "");
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else if (Successors.size() == 2) {
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drawEdge(Block, Successors.front(), false, "T");
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drawEdge(Block, Successors.back(), false, "F");
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} else {
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unsigned SuccessorNumber = 0;
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for (auto *Successor : Successors)
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drawEdge(Block, Successor, false, Twine(SuccessorNumber++));
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}
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}
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void VPlanPrinter::dumpBasicBlock(const VPBasicBlock *BasicBlock) {
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OS << Indent << getUID(BasicBlock) << " [label =\n";
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bumpIndent(1);
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OS << Indent << "\"" << DOT::EscapeString(BasicBlock->getName()) << ":\\n\"";
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bumpIndent(1);
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for (const VPRecipeBase &Recipe : *BasicBlock)
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Recipe.print(OS, Indent);
|
|
|
|
// Dump the condition bit.
|
|
const VPValue *CBV = BasicBlock->getCondBit();
|
|
if (CBV) {
|
|
OS << " +\n" << Indent << " \"CondBit: ";
|
|
if (const VPInstruction *CBI = dyn_cast<VPInstruction>(CBV)) {
|
|
CBI->printAsOperand(OS);
|
|
OS << " (" << DOT::EscapeString(CBI->getParent()->getName()) << ")\\l\"";
|
|
} else
|
|
CBV->printAsOperand(OS);
|
|
}
|
|
|
|
bumpIndent(-2);
|
|
OS << "\n" << Indent << "]\n";
|
|
dumpEdges(BasicBlock);
|
|
}
|
|
|
|
void VPlanPrinter::dumpRegion(const VPRegionBlock *Region) {
|
|
OS << Indent << "subgraph " << getUID(Region) << " {\n";
|
|
bumpIndent(1);
|
|
OS << Indent << "fontname=Courier\n"
|
|
<< Indent << "label=\""
|
|
<< DOT::EscapeString(Region->isReplicator() ? "<xVFxUF> " : "<x1> ")
|
|
<< DOT::EscapeString(Region->getName()) << "\"\n";
|
|
// Dump the blocks of the region.
|
|
assert(Region->getEntry() && "Region contains no inner blocks.");
|
|
for (const VPBlockBase *Block : depth_first(Region->getEntry()))
|
|
dumpBlock(Block);
|
|
bumpIndent(-1);
|
|
OS << Indent << "}\n";
|
|
dumpEdges(Region);
|
|
}
|
|
|
|
void VPlanPrinter::printAsIngredient(raw_ostream &O, Value *V) {
|
|
std::string IngredientString;
|
|
raw_string_ostream RSO(IngredientString);
|
|
if (auto *Inst = dyn_cast<Instruction>(V)) {
|
|
if (!Inst->getType()->isVoidTy()) {
|
|
Inst->printAsOperand(RSO, false);
|
|
RSO << " = ";
|
|
}
|
|
RSO << Inst->getOpcodeName() << " ";
|
|
unsigned E = Inst->getNumOperands();
|
|
if (E > 0) {
|
|
Inst->getOperand(0)->printAsOperand(RSO, false);
|
|
for (unsigned I = 1; I < E; ++I)
|
|
Inst->getOperand(I)->printAsOperand(RSO << ", ", false);
|
|
}
|
|
} else // !Inst
|
|
V->printAsOperand(RSO, false);
|
|
RSO.flush();
|
|
O << DOT::EscapeString(IngredientString);
|
|
}
|
|
|
|
void VPWidenRecipe::print(raw_ostream &O, const Twine &Indent) const {
|
|
O << " +\n" << Indent << "\"WIDEN\\l\"";
|
|
for (auto &Instr : make_range(Begin, End))
|
|
O << " +\n" << Indent << "\" " << VPlanIngredient(&Instr) << "\\l\"";
|
|
}
|
|
|
|
void VPWidenIntOrFpInductionRecipe::print(raw_ostream &O,
|
|
const Twine &Indent) const {
|
|
O << " +\n" << Indent << "\"WIDEN-INDUCTION";
|
|
if (Trunc) {
|
|
O << "\\l\"";
|
|
O << " +\n" << Indent << "\" " << VPlanIngredient(IV) << "\\l\"";
|
|
O << " +\n" << Indent << "\" " << VPlanIngredient(Trunc) << "\\l\"";
|
|
} else
|
|
O << " " << VPlanIngredient(IV) << "\\l\"";
|
|
}
|
|
|
|
void VPWidenPHIRecipe::print(raw_ostream &O, const Twine &Indent) const {
|
|
O << " +\n" << Indent << "\"WIDEN-PHI " << VPlanIngredient(Phi) << "\\l\"";
|
|
}
|
|
|
|
void VPBlendRecipe::print(raw_ostream &O, const Twine &Indent) const {
|
|
O << " +\n" << Indent << "\"BLEND ";
|
|
Phi->printAsOperand(O, false);
|
|
O << " =";
|
|
if (!User) {
|
|
// Not a User of any mask: not really blending, this is a
|
|
// single-predecessor phi.
|
|
O << " ";
|
|
Phi->getIncomingValue(0)->printAsOperand(O, false);
|
|
} else {
|
|
for (unsigned I = 0, E = User->getNumOperands(); I < E; ++I) {
|
|
O << " ";
|
|
Phi->getIncomingValue(I)->printAsOperand(O, false);
|
|
O << "/";
|
|
User->getOperand(I)->printAsOperand(O);
|
|
}
|
|
}
|
|
O << "\\l\"";
|
|
}
|
|
|
|
void VPReplicateRecipe::print(raw_ostream &O, const Twine &Indent) const {
|
|
O << " +\n"
|
|
<< Indent << "\"" << (IsUniform ? "CLONE " : "REPLICATE ")
|
|
<< VPlanIngredient(Ingredient);
|
|
if (AlsoPack)
|
|
O << " (S->V)";
|
|
O << "\\l\"";
|
|
}
|
|
|
|
void VPPredInstPHIRecipe::print(raw_ostream &O, const Twine &Indent) const {
|
|
O << " +\n"
|
|
<< Indent << "\"PHI-PREDICATED-INSTRUCTION " << VPlanIngredient(PredInst)
|
|
<< "\\l\"";
|
|
}
|
|
|
|
void VPWidenMemoryInstructionRecipe::print(raw_ostream &O,
|
|
const Twine &Indent) const {
|
|
O << " +\n" << Indent << "\"WIDEN " << VPlanIngredient(&Instr);
|
|
if (User) {
|
|
O << ", ";
|
|
User->getOperand(0)->printAsOperand(O);
|
|
}
|
|
O << "\\l\"";
|
|
}
|
|
|
|
template void DomTreeBuilder::Calculate<VPDominatorTree>(VPDominatorTree &DT);
|