forked from OSchip/llvm-project
175 lines
4.2 KiB
C++
175 lines
4.2 KiB
C++
//==- AMDGPUArgumentrUsageInfo.h - Function Arg Usage Info -------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUARGUMENTUSAGEINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUARGUMENTUSAGEINFO_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Pass.h"
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namespace llvm {
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class Function;
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class raw_ostream;
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class GCNSubtarget;
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class TargetMachine;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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struct ArgDescriptor {
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private:
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friend struct AMDGPUFunctionArgInfo;
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friend class AMDGPUArgumentUsageInfo;
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union {
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unsigned Register;
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unsigned StackOffset;
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};
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bool IsStack : 1;
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bool IsSet : 1;
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ArgDescriptor(unsigned Val = 0, bool IsStack = false, bool IsSet = false)
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: Register(Val), IsStack(IsStack), IsSet(IsSet) {}
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public:
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static ArgDescriptor createRegister(unsigned Reg) {
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return ArgDescriptor(Reg, false, true);
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}
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static ArgDescriptor createStack(unsigned Reg) {
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return ArgDescriptor(Reg, true, true);
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}
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bool isSet() const {
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return IsSet;
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}
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explicit operator bool() const {
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return isSet();
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}
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bool isRegister() const {
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return !IsStack;
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}
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unsigned getRegister() const {
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assert(!IsStack);
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return Register;
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}
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unsigned getStackOffset() const {
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assert(IsStack);
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return StackOffset;
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}
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void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const;
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};
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inline raw_ostream &operator<<(raw_ostream &OS, const ArgDescriptor &Arg) {
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Arg.print(OS);
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return OS;
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}
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struct AMDGPUFunctionArgInfo {
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enum PreloadedValue {
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// SGPRS:
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PRIVATE_SEGMENT_BUFFER = 0,
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DISPATCH_PTR = 1,
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QUEUE_PTR = 2,
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KERNARG_SEGMENT_PTR = 3,
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DISPATCH_ID = 4,
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FLAT_SCRATCH_INIT = 5,
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WORKGROUP_ID_X = 10,
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WORKGROUP_ID_Y = 11,
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WORKGROUP_ID_Z = 12,
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PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 14,
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IMPLICIT_BUFFER_PTR = 15,
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IMPLICIT_ARG_PTR = 16,
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// VGPRS:
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WORKITEM_ID_X = 17,
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WORKITEM_ID_Y = 18,
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WORKITEM_ID_Z = 19,
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FIRST_VGPR_VALUE = WORKITEM_ID_X
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};
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// Kernel input registers setup for the HSA ABI in allocation order.
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// User SGPRs in kernels
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// XXX - Can these require argument spills?
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ArgDescriptor PrivateSegmentBuffer;
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ArgDescriptor DispatchPtr;
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ArgDescriptor QueuePtr;
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ArgDescriptor KernargSegmentPtr;
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ArgDescriptor DispatchID;
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ArgDescriptor FlatScratchInit;
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ArgDescriptor PrivateSegmentSize;
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// System SGPRs in kernels.
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ArgDescriptor WorkGroupIDX;
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ArgDescriptor WorkGroupIDY;
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ArgDescriptor WorkGroupIDZ;
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ArgDescriptor WorkGroupInfo;
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ArgDescriptor PrivateSegmentWaveByteOffset;
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// Pointer with offset from kernargsegmentptr to where special ABI arguments
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// are passed to callable functions.
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ArgDescriptor ImplicitArgPtr;
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// Input registers for non-HSA ABI
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ArgDescriptor ImplicitBufferPtr = 0;
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// VGPRs inputs. These are always v0, v1 and v2 for entry functions.
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ArgDescriptor WorkItemIDX;
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ArgDescriptor WorkItemIDY;
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ArgDescriptor WorkItemIDZ;
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std::pair<const ArgDescriptor *, const TargetRegisterClass *>
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getPreloadedValue(PreloadedValue Value) const;
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};
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class AMDGPUArgumentUsageInfo : public ImmutablePass {
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private:
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static const AMDGPUFunctionArgInfo ExternFunctionInfo;
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DenseMap<const Function *, AMDGPUFunctionArgInfo> ArgInfoMap;
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public:
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static char ID;
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AMDGPUArgumentUsageInfo() : ImmutablePass(ID) { }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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}
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bool doInitialization(Module &M) override;
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bool doFinalization(Module &M) override;
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void print(raw_ostream &OS, const Module *M = nullptr) const override;
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void setFuncArgInfo(const Function &F, const AMDGPUFunctionArgInfo &ArgInfo) {
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ArgInfoMap[&F] = ArgInfo;
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}
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const AMDGPUFunctionArgInfo &lookupFuncArgInfo(const Function &F) const {
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auto I = ArgInfoMap.find(&F);
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if (I == ArgInfoMap.end()) {
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assert(F.isDeclaration());
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return ExternFunctionInfo;
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}
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return I->second;
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}
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};
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} // end namespace llvm
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#endif
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