forked from OSchip/llvm-project
00463119a5
Summary: There is no change to the restrictions, just the result register is stored once in the encoding rather than twice. The rt field is zero in MIPS32r6/MIPS64r6. Depends on D4119 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4120 llvm-svn: 211019 |
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invalid-mips1-wrong-error.s | ||
invalid-mips1.s | ||
invalid-mips2.s | ||
invalid-mips3-wrong-error.s | ||
invalid-mips3.s | ||
invalid-mips4-wrong-error.s | ||
invalid-mips4.s | ||
invalid-mips5-wrong-error.s | ||
invalid-mips5.s | ||
invalid-mips32-wrong-error.s | ||
invalid-mips64.s | ||
invalid.s | ||
relocations.s | ||
valid-xfail.s | ||
valid.s |