forked from OSchip/llvm-project
172 lines
7.1 KiB
C++
172 lines
7.1 KiB
C++
//===-- xray_mips.cpp -------------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is a part of XRay, a dynamic runtime instrumentation system.
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//
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// Implementation of MIPS-specific routines (32-bit).
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//
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//===----------------------------------------------------------------------===//
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#include "sanitizer_common/sanitizer_common.h"
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#include "xray_defs.h"
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#include "xray_interface_internal.h"
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#include <atomic>
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namespace __xray {
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// The machine codes for some instructions used in runtime patching.
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enum PatchOpcodes : uint32_t {
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PO_ADDIU = 0x24000000, // addiu rt, rs, imm
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PO_SW = 0xAC000000, // sw rt, offset(sp)
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PO_LUI = 0x3C000000, // lui rs, %hi(address)
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PO_ORI = 0x34000000, // ori rt, rs, %lo(address)
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PO_JALR = 0x0000F809, // jalr rs
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PO_LW = 0x8C000000, // lw rt, offset(address)
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PO_B44 = 0x1000000b, // b #44
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PO_NOP = 0x0, // nop
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};
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enum RegNum : uint32_t {
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RN_T0 = 0x8,
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RN_T9 = 0x19,
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RN_RA = 0x1F,
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RN_SP = 0x1D,
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};
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inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs,
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uint32_t Rt,
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uint32_t Imm) XRAY_NEVER_INSTRUMENT {
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return (Opcode | Rs << 21 | Rt << 16 | Imm);
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}
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inline static uint32_t
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encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
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uint32_t Imm) XRAY_NEVER_INSTRUMENT {
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return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
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}
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inline static bool patchSled(const bool Enable, const uint32_t FuncId,
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const XRaySledEntry &Sled,
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void (*TracingHook)()) XRAY_NEVER_INSTRUMENT {
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// When |Enable| == true,
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// We replace the following compile-time stub (sled):
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//
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// xray_sled_n:
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// B .tmpN
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// 11 NOPs (44 bytes)
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// .tmpN
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// ADDIU T9, T9, 44
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//
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// With the following runtime patch:
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//
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// xray_sled_n (32-bit):
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// addiu sp, sp, -8 ;create stack frame
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// nop
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// sw ra, 4(sp) ;save return address
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// sw t9, 0(sp) ;save register t9
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// lui t9, %hi(__xray_FunctionEntry/Exit)
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// ori t9, t9, %lo(__xray_FunctionEntry/Exit)
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// lui t0, %hi(function_id)
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// jalr t9 ;call Tracing hook
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// ori t0, t0, %lo(function_id) ;pass function id (delay slot)
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// lw t9, 0(sp) ;restore register t9
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// lw ra, 4(sp) ;restore return address
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// addiu sp, sp, 8 ;delete stack frame
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//
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// We add 44 bytes to t9 because we want to adjust the function pointer to
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// the actual start of function i.e. the address just after the noop sled.
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// We do this because gp displacement relocation is emitted at the start of
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// of the function i.e after the nop sled and to correctly calculate the
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// global offset table address, t9 must hold the address of the instruction
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// containing the gp displacement relocation.
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// FIXME: Is this correct for the static relocation model?
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//
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// Replacement of the first 4-byte instruction should be the last and atomic
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// operation, so that the user code which reaches the sled concurrently
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// either jumps over the whole sled, or executes the whole sled when the
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// latter is ready.
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//
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// When |Enable|==false, we set back the first instruction in the sled to be
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// B #44
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uint32_t *Address = reinterpret_cast<uint32_t *>(Sled.address());
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if (Enable) {
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uint32_t LoTracingHookAddr =
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reinterpret_cast<int32_t>(TracingHook) & 0xffff;
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uint32_t HiTracingHookAddr =
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(reinterpret_cast<int32_t>(TracingHook) >> 16) & 0xffff;
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uint32_t LoFunctionID = FuncId & 0xffff;
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uint32_t HiFunctionID = (FuncId >> 16) & 0xffff;
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Address[2] = encodeInstruction(PatchOpcodes::PO_SW, RegNum::RN_SP,
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RegNum::RN_RA, 0x4);
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Address[3] = encodeInstruction(PatchOpcodes::PO_SW, RegNum::RN_SP,
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RegNum::RN_T9, 0x0);
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Address[4] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9,
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HiTracingHookAddr);
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Address[5] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9,
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RegNum::RN_T9, LoTracingHookAddr);
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Address[6] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0,
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HiFunctionID);
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Address[7] = encodeSpecialInstruction(PatchOpcodes::PO_JALR, RegNum::RN_T9,
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0x0, RegNum::RN_RA, 0X0);
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Address[8] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T0,
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RegNum::RN_T0, LoFunctionID);
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Address[9] = encodeInstruction(PatchOpcodes::PO_LW, RegNum::RN_SP,
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RegNum::RN_T9, 0x0);
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Address[10] = encodeInstruction(PatchOpcodes::PO_LW, RegNum::RN_SP,
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RegNum::RN_RA, 0x4);
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Address[11] = encodeInstruction(PatchOpcodes::PO_ADDIU, RegNum::RN_SP,
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RegNum::RN_SP, 0x8);
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uint32_t CreateStackSpaceInstr = encodeInstruction(
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PatchOpcodes::PO_ADDIU, RegNum::RN_SP, RegNum::RN_SP, 0xFFF8);
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std::atomic_store_explicit(
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reinterpret_cast<std::atomic<uint32_t> *>(Address),
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uint32_t(CreateStackSpaceInstr), std::memory_order_release);
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} else {
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std::atomic_store_explicit(
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reinterpret_cast<std::atomic<uint32_t> *>(Address),
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uint32_t(PatchOpcodes::PO_B44), std::memory_order_release);
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}
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return true;
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}
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bool patchFunctionEntry(const bool Enable, const uint32_t FuncId,
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const XRaySledEntry &Sled,
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void (*Trampoline)()) XRAY_NEVER_INSTRUMENT {
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return patchSled(Enable, FuncId, Sled, Trampoline);
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}
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bool patchFunctionExit(const bool Enable, const uint32_t FuncId,
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const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
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return patchSled(Enable, FuncId, Sled, __xray_FunctionExit);
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}
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bool patchFunctionTailExit(const bool Enable, const uint32_t FuncId,
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const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
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// FIXME: In the future we'd need to distinguish between non-tail exits and
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// tail exits for better information preservation.
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return patchSled(Enable, FuncId, Sled, __xray_FunctionExit);
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}
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bool patchCustomEvent(const bool Enable, const uint32_t FuncId,
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const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
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// FIXME: Implement in mips?
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return false;
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}
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bool patchTypedEvent(const bool Enable, const uint32_t FuncId,
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const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
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// FIXME: Implement in mips?
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return false;
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}
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} // namespace __xray
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extern "C" void __xray_ArgLoggerEntry() XRAY_NEVER_INSTRUMENT {
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// FIXME: this will have to be implemented in the trampoline assembly file
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}
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