Commit Graph

6 Commits

Author SHA1 Message Date
Bill Seurer 8be14f11ce [PowerPC] This revision adds 68 of the missing "Predefined Functions for Vector Programming" from appendix A of the OpenPOWER ABI for Linux Supplement document.
I also added tests for the new functions and updated another test that was looking for specific line numbers in error messages from altivec.h.

https://llvm.org/bugs/show_bug.cgi?id=23679

http://reviews.llvm.org/D10131

llvm-svn: 239066
2015-06-04 18:45:44 +00:00
Kit Barton 5944ee2179 This patch adds support for the vector quadword add/sub instructions introduced
in POWER8.

These are the Clang-related changes for http://reviews.llvm.org/D9081

vadduqm
vaddeuqm
vaddcuq
vaddecuq
vsubuqm
vsubeuqm
vsubcuq
vsubecuq
All builtins are added in altivec.h, and guarded with the POWER8_VECTOR and
powerpc64 macros.



http://reviews.llvm.org/D9903

llvm-svn: 238145
2015-05-25 15:52:45 +00:00
Bill Schmidt 41e14c4dfa [PPC64] Add vector pack/unpack support from ISA 2.07
This patch adds support for the following new instructions in the
Power ISA 2.07:

  vpksdss
  vpksdus
  vpkudus
  vpkudum
  vupkhsw
  vupklsw

These instructions are available through the vec_packs, vec_packsu,
vec_unpackh, and vec_unpackl built-in interfaces.  These are
lane-sensitive instructions, so the built-ins have different
implementations for big- and little-endian, and the instructions must
be marked as killing the vector swap optimization for now.

The first three instructions perform saturating pack operations.  The
fourth performs a modulo pack operation, which means it can be
represented with a vector shuffle, and conversely the appropriate
vector shuffles may cause this instruction to be generated.  The other
instructions are only generated via built-in support for now.

I noticed during patch preparation that the macro __VSX__ was not
previously predefined when the power8-vector or direct-move features
are requested.  This is an error, and I've corrected that here as
well.

Appropriate tests have been added.

There is a companion patch to llvm for the rest of this support.

llvm-svn: 237500
2015-05-16 01:02:25 +00:00
Kit Barton 8553bec911 Add builtins for the 64-bit vector integer arithmetic instructions added in POWER8.
These are the Clang-related changes for the instructions added to LLVM in http://reviews.llvm.org/D7959.

Phabricator review: http://reviews.llvm.org/D8041

llvm-svn: 231931
2015-03-11 15:57:19 +00:00
Bill Schmidt cee13a2712 [PowerPC] Add VSX builtins for vec_div
This patch adds builtin support for xvdivdp and xvdivsp, along with a
new test case.  The builtins are accessed using vec_div in altivec.h.
Builtins are listed (mostly) alphabetically there, so inserting these
changed the line numbers for deprecation warnings tested in
test/Headers/altivec-intrin.c.

There is a companion patch for LLVM.

llvm-svn: 221984
2014-11-14 12:10:51 +00:00
Bill Schmidt cad3a5f7d4 [PATCH][Power] Fix (and deprecate) vec_lvsl and vec_lvsr for little endian
The use of the vec_lvsl and vec_lvsr interfaces are discouraged for
little endian targets since Power8 hardware is a minimum requirement,
and Power8 provides reasonable performance for unaligned vector loads
and stores.  Up till now we have not provided "correct" (i.e., big-
endian-compatible) code generation for these interfaces, as to do so
produces poorly performing code.  However, this has become the source
of too many questions.

With this patch, LLVM will now produce compatible code for these
interfaces, but will also produce a deprecation warning message for
PPC64LE when one of them is used.  This should make the porting direction
clearer to programmers.  A similar patch has recently been committed to
GCC.

This patch includes a test for the warning message.  There is a companion
patch that adds two unit tests to projects/test-suite.

llvm-svn: 219137
2014-10-06 19:02:20 +00:00