maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
182,974 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

12 Commits

Author SHA1 Message Date
Matt Arsenault e9fa3b8e6b R600/SI: Implement less wrong f32 fdiv 
Assuming single precision denormals and accurate sqrt/div are not
reported, this passes the OpenCL conformance test.

llvm-svn: 213089
 2014-07-15 20:18:31 +00:00
Tom Stellard 70f13dba15 R600/SI: Use -verify-machineinstrs for most tests 
We can't enable the verifier for tests with SI_IF and SI_ELSE, because
these instructions are always followed by a COPY which copies their
result to the next basic block.  This violates the machine verifier's
rule that non-terminators can not folow terminators.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 192366
 2013-10-10 17:11:46 +00:00
Vincent Lejeune 7e2c83256b R600: Non vector only instruction can be scheduled on trans unit 
llvm-svn: 189980
 2013-09-04 19:53:46 +00:00
Tom Stellard a92ff87929 R600: Expand vector float operations for both SI and R600 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 188596
 2013-08-16 23:51:24 +00:00
Tom Stellard 0344cdfe39 R600: Add 64-bit float load/store support 
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions

Tom Stellard:
  - Mark vec2 operations as expand.  The addition of a vec2 register
    class made them all legal.

Patch by: Dmitry Cherkassov

Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
llvm-svn: 187582
 2013-08-01 15:23:42 +00:00
Tom Stellard ca69a53bae Revert "R600: Non vector only instruction can be scheduled on trans unit" 
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.

llvm-svn: 187526
 2013-07-31 20:43:27 +00:00
Vincent Lejeune df18804e26 R600: Non vector only instruction can be scheduled on trans unit 
llvm-svn: 187514
 2013-07-31 19:31:56 +00:00
Tom Stellard 1e80309ebe R600: Use KCache for kernel arguments 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186918
 2013-07-23 01:48:18 +00:00
Vincent Lejeune 77a8352476 R600: Support schedule and packetization of trans-only inst 
llvm-svn: 185268
 2013-06-29 19:32:43 +00:00
Vincent Lejeune 3d5118ca40 R600: Use bottom up scheduling algorithm 
llvm-svn: 182129
 2013-05-17 16:50:56 +00:00
Vincent Lejeune f97af796a9 R600: Prettier asmPrint of Alu 
llvm-svn: 180956
 2013-05-02 21:52:30 +00:00
Tom Stellard 5a6b0d828b R600: Reorganize lit tests and document how they should be organized 
llvm-svn: 179828
 2013-04-19 02:10:53 +00:00