Commit Graph

148752 Commits

Author SHA1 Message Date
Eugene Zelenko ff9b0e2df2 [IR] Rollback changes in r302744 which caused buildbots failures.
llvm-svn: 302745
2017-05-10 23:53:40 +00:00
Eugene Zelenko eba7e4ec55 [IR] Fix some Clang-tidy modernize-use-using warnings; other minor fixes (NFC).
llvm-svn: 302744
2017-05-10 23:41:30 +00:00
Davide Italiano 1e8c59a8ac [PHIElimination] Use the same name for DEBUG_TYPE and pass name.
In an attempt to reduce the confusion.

llvm-svn: 302742
2017-05-10 23:13:26 +00:00
Sanjay Patel 40a87a909b [InstCombine] remove fold that swaps xor/or with constants; NFCI
// (X ^ C1) | C2 --> (X | C2) ^ (C1&~C2)

This canonicalization was added at:
https://reviews.llvm.org/rL7264 

By moving xors out/down, we can more easily combine constants. I'm adding
tests that do not change with this patch, so we can verify that those kinds
of transforms are still happening.

This is no-functional-change-intended because there's a later fold:
// (X^C)|Y -> (X|Y)^C iff Y&C == 0
...and demanded-bits appears to guarantee that any fold that would have
hit the fold we're removing here would be caught by that 2nd fold.

Similar reasoning was used in:
https://reviews.llvm.org/rL299384

The larger motivation for removing this code is that it could interfere with 
the fix for PR32706:
https://bugs.llvm.org/show_bug.cgi?id=32706

Ie, we're not checking if the 'xor' is actually a 'not', so we could reverse
a 'not' optimization and cause an infinite loop by altering an 'xor X, -1'. 

Differential Revision: https://reviews.llvm.org/D33050

llvm-svn: 302733
2017-05-10 21:33:55 +00:00
Matt Arsenault 3c5e4237c6 AMDGPU: Make some packed shuffles free
VOP3P instructions can encode access to either
half of the register.

llvm-svn: 302730
2017-05-10 21:29:33 +00:00
Matt Arsenault acdc7659cc AMDGPU: Add new subtarget features for gfx9 flat instructions
Flat instructions gain an immediate offset, and 2 new
sets of segment specific flat instructions are added.

llvm-svn: 302729
2017-05-10 21:19:05 +00:00
Craig Topper c51d05369a [ConstantRange] Fix the early out in ConstantRange::multiply for positive numbers to really do what the comment says
r271020 added an early out to skip the signed multiply portion of ConstantRange::multiply. The comment says we don't need to do signed multiply if the range is only positive numbers, but the implemented check only ensures that the start of the range is positive. It doesn't look at the end of the range.

This patch checks the end of the range instead. Because Upper is one more than the end we have to see if its positive or if its one past the last positive number.

llvm-svn: 302717
2017-05-10 20:01:48 +00:00
Craig Topper ef0114c4f0 [APInt] Add negate helper method to implement twos complement. Use it to shorten code.
llvm-svn: 302716
2017-05-10 20:01:38 +00:00
Davide Italiano dc435325a8 [NewGVN] Introduce a definesNoMemory() helper and use it.
This is nice as is, but it will be used in my next patch to
fix a bug. Suggested by Daniel Berlin.

llvm-svn: 302714
2017-05-10 19:57:43 +00:00
Nirav Dave a38c049fc5 [SDAG] Relax conditions under stores of loaded values can be merged
Summary:

Allow consecutive stores whose values come from consecutive loads to
merged in the presense of other uses of the loads. Previously this was
disallowed as in general the merged load cannot be shared with the
other uses. Merging N stores into 1 may cause as many as N redundant
loads. However in the context of caching this should have neglible
affect on memory pressure and reduce instruction count making it
almost always a win.

Fixes PR32086.

Reviewers: spatel, jyknight, andreadb, hfinkel, efriedma

Reviewed By: efriedma

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30471

llvm-svn: 302712
2017-05-10 19:53:41 +00:00
Teresa Johnson 94624aca2a Ensure non-null ProfileSummaryInfo passed to ModuleSummaryIndex builder
This fixes a ubsan bot failure after r302597, which made getProfileCount
non-static, but ended up invoking it on a null ProfileSummaryInfo object
in some cases from buildModuleSummaryIndex.

Most testing passed because the non-static getProfileCount currently
doesn't access any member variables, but I found this when testing a
follow on patch (D32877) that adds a member variable access.

llvm-svn: 302705
2017-05-10 18:52:16 +00:00
Craig Topper ecb97da108 [APInt] Make toString use udivrem instead of calling the divide helper method directly. Do a better job of reusing allocations while looping. NFCI
This lets toString take advantage of the degenerate case checks in udivrem and is just generally cleaner.

One minor downside of this is that the divisor APInt now needs to be the same size as Tmp which requires an additional allocation. But we were doing a poor job of reusing allocations before so the new code should still be an improvement.

llvm-svn: 302704
2017-05-10 18:15:24 +00:00
Craig Topper 6271bc7146 [APInt] Use uint32_t instead of unsigned for the storage type throughout the divide code. Use Lo_32/Hi_32/Make_64 helpers instead of casts and shifts. NFCI
llvm-svn: 302703
2017-05-10 18:15:20 +00:00
Craig Topper f86b9d5063 [APInt] Use getRawData to slightly simplify some code.
llvm-svn: 302702
2017-05-10 18:15:17 +00:00
Craig Topper 93eabae4aa [APInt] Remove check for single word since single word was handled earlier in the function. NFC
llvm-svn: 302701
2017-05-10 18:15:14 +00:00
Craig Topper 9bbae50d83 [ConstantRange] Add test case showing a case where we pick too large of a range for multiply after r271020.
llvm-svn: 302700
2017-05-10 18:15:06 +00:00
Amaury Sechet 197685c6d8 Small refactoring in DAGCombine. NFC
llvm-svn: 302699
2017-05-10 17:58:28 +00:00
Sanjay Patel 0b24b7ef72 [InstSimplify, InstCombine] move 'or' simplification tests; NFC
Surprisingly, I don't think these are redundant for InstSimplify. 
They were just misplaced as InstCombine tests.

llvm-svn: 302684
2017-05-10 15:57:47 +00:00
Simon Pilgrim 3fc619a49c [X86][SSE] Check vec_set BUILD_VECTOR tests on both 32 and 64-bit targets
llvm-svn: 302683
2017-05-10 15:52:59 +00:00
Quentin Colombet 307e29124c [AArch64][RegisterBankInfo] Change the default mapping of fp stores.
For stores, check if the stored value is defined by a floating point
instruction and if yes, we return a default mapping with FPR instead
of GPR.

llvm-svn: 302679
2017-05-10 15:19:41 +00:00
Amara Emerson 816542ceb3 [AArch64] Enable use of reduction intrinsics.
The new experimental reduction intrinsics can now be used, so I'm enabling this
for AArch64. We will need this for SVE anyway, so it makes sense to do this for
NEON reductions as well.

The existing code to match shufflevector patterns are replaced with a direct
lowering of the reductions to AArch64-specific nodes. Tests updated with the
new, simpler, representation.

Differential Revision: https://reviews.llvm.org/D32247

llvm-svn: 302678
2017-05-10 15:15:38 +00:00
Sanjay Patel 30a7157372 [InstCombine] remove redundant tests
The first test in this file is duplicated exactly in and.ll -> test33.
We have commuted and vector variants there too.

The second test is a composite of 2 folds. The first fold is tested
independently in add.ll -> flip_and_mask (including vector variant).
After that transform fires, the IR is identical to the first transform.

llvm-svn: 302676
2017-05-10 14:54:49 +00:00
Sanjay Patel beac508fc9 [InstCombine] fix auto-generated FileCheck-captured variable refs
The script at utils/update_test_checks.py has (had?) a bug when variables
start with the same sequence of letters (clearly, not all of the time).

llvm-svn: 302674
2017-05-10 14:40:04 +00:00
Sanjay Patel 3d8905f3a0 [InstCombine] fix typo in test comment; NFC
llvm-svn: 302669
2017-05-10 14:25:23 +00:00
Ulrich Weigand 93b369ed11 [SystemZ] Add miscellaneous instructions
This adds a few missing instructions for the assembler and
disassembler.  Those should be the last missing general-
purpose (Chapter 7) instructions for the z10 ISA.

llvm-svn: 302667
2017-05-10 14:20:15 +00:00
Ulrich Weigand d3604dc72c [SystemZ] Add missing arithmetic instructions
This adds the remaining general arithmetic instructions
for assembler / disassembler use.  Most of these are not
useful for codegen; a few might be, and those are listed
in the README.txt for future improvements.

llvm-svn: 302665
2017-05-10 14:18:47 +00:00
Sam Clegg c0d76649d4 [llvm-readobj] Improve errors on invalid binary
The previous code was discarding the error message from
createBinary() by calling errorToErrorCode().
This meant that such error were always reported unhelpfully
as "Invalid data was encountered while parsing the file".

Other tools such as llvm-objdump already produce a more
the error message in this case.

Differential Revision: https://reviews.llvm.org/D32985

llvm-svn: 302664
2017-05-10 14:18:11 +00:00
Michael Zuckerman ff29879f2e chang type from 'int' to 'size_t'. This will fix revision number 302652
llvm-svn: 302660
2017-05-10 14:00:57 +00:00
Sanjay Patel 2e069f250a [InstCombine] add (ashr (shl i32 X, 31), 31), 1 --> and (not X), 1
This is another step towards favoring 'not' ops over random 'xor' in IR:
https://bugs.llvm.org/show_bug.cgi?id=32706

This transformation may have occurred in longer IR sequences using computeKnownBits,
but that could be much more expensive to calculate.

As the scalar result shows, we do not currently favor 'not' in all cases. The 'not'
created by the transform is transformed again (unnecessarily). Vectors don't have
this problem because vectors are (wrongly) excluded from several other combines.

llvm-svn: 302659
2017-05-10 13:56:52 +00:00
Serge Guelton 778ece82ae Use explicit false instead of casted nullptr. NFC.
llvm-svn: 302656
2017-05-10 13:24:17 +00:00
Serge Guelton c9668165d6 Use clang++-3.5 compatible initializer_list constructor
Otherwise, a warning is issued.

llvm-svn: 302655
2017-05-10 13:23:47 +00:00
Michael Zuckerman 1f1a912c60 [LLVM][inline-asm] Altmacro string escape character '!'
This patch is the fourth patch in a series of reviews for the Altmacro feature. 
This patch introduces a new escape character '!' and it depends on D32701.

according to https://sourceware.org/binutils/docs/as/Altmacro.html:
"single-character string escape
To include any single character literally in a string (even if the character would otherwise have some special meaning), you can prefix the character with !' (an exclamation mark). For example, you can write <4.3 !> 5.4!!>' to get the literal text `4.3 > 5.4!'. "

Differential Revision: https://reviews.llvm.org/D32792

llvm-svn: 302652
2017-05-10 13:08:11 +00:00
Simon Pilgrim cd4d913336 [DAGCombiner] Dropped explicit (sra 0, x) -> 0 and (sra -1, x) -> 0 folds.
These are both handled (and tested) by the earlier ComputeNumSignBits == EltSizeInBits fold.

llvm-svn: 302651
2017-05-10 13:06:26 +00:00
Mikael Holmen 21c867c26e [IfConversion] Add missing check in IfConversion/canFallThroughTo
Summary:
When trying to figure out if MBB could fallthrough to ToMBB (possibly by
falling through a bunch of other MBBs) we didn't actually check if there
was fallthrough between the last two blocks in the chain.

Reviewers: kparzysz, iteratee, MatzeB

Reviewed By: kparzysz, iteratee

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D32996

llvm-svn: 302650
2017-05-10 13:06:13 +00:00
Jonas Paulsson 11d251c05c [SystemZ] Implement getRepRegClassFor()
This method must return a valid register class, or the list-ilp isel
scheduler will crash. For MVT::Untyped nullptr was previously returned, but
now ADDR128BitRegClass is returned instead. This is needed just as long as
list-ilp (and probably also list-hybrid) is still there.

Review: Ulrich Weigand, A Trick
https://reviews.llvm.org/D32802

llvm-svn: 302649
2017-05-10 13:03:25 +00:00
Dmitry Preobrazhensky da61a7f9ef [AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in disassembler output
See bug 32927: https://bugs.llvm.org//show_bug.cgi?id=32927

Reviewers: vpykhtin, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D32913

llvm-svn: 302648
2017-05-10 13:00:28 +00:00
Igor Breger 8e5e40862a [GlobalISel][X86] Split test file. NFC
llvm-svn: 302647
2017-05-10 12:58:31 +00:00
Ulrich Weigand c7eb5a95b2 [SystemZ] Add decimal integer instructions
This adds the set of decimal integer (BCD) instructions for
assembler / disassembler use.

llvm-svn: 302646
2017-05-10 12:42:45 +00:00
Ulrich Weigand 33a441adf9 [SystemZ] Add crypto instructions
This adds the set of message-security assist instructions for
assembler / disassembler use.

llvm-svn: 302645
2017-05-10 12:42:00 +00:00
Ulrich Weigand 435cd1a3e4 [SystemZ] Add translate/convert instructions
This adds the set of character-set translate and convert instructions
for assembler / disassembler use.

llvm-svn: 302644
2017-05-10 12:41:12 +00:00
Ulrich Weigand eb17909536 [SystemZ] Add missing memory/string instructions
This adds a number of missing memory and string instructions
for assembler / disassembler use.

llvm-svn: 302643
2017-05-10 12:40:15 +00:00
Ulrich Weigand 52461726dd [SystemZ] Reformat assembler/disassembler tests
The assembler and disassmebler test cases started out formatted and
sorted in a particular way, but this got lost over time as patches
were added.  Reformat them again.  NFC.

llvm-svn: 302642
2017-05-10 12:39:11 +00:00
Simon Pilgrim c29af824bf [DAGCombiner] Add vector support to fold (shl/srl 0, x) -> 0
llvm-svn: 302641
2017-05-10 12:34:27 +00:00
Chandler Carruth f3bd8ddedb Revert r301950: SpeculativeExecution: Stop using whitelist for costs
This pass doesn't correctly handle testing for when it is legal to hoist
arbitrary instructions. The whitelist happens to make it safe, so before
it is removed the pass's legality checks will need to be enhanced.

Details have been added to the code review thread for the patch.

llvm-svn: 302640
2017-05-10 12:30:07 +00:00
Martin Storsjo 605b0466ea [AArch64] Fix a comment to match the code. NFC.
For the ELF case, the default/preferred form is the generic one, not
the short one as used for Apple - fix the comment to say so. Currently
it is a copy-paste typo.

Make the comments on the darwin default a bit more verbose.

Use enum names instead of literal 0/1 to further increase readability
and reduce fragility.

Differential Revision: https://reviews.llvm.org/D32963

llvm-svn: 302634
2017-05-10 10:51:32 +00:00
Amara Emerson 836b0f48c1 Add a late IR expansion pass for the experimental reduction intrinsics.
This pass uses a new target hook to decide whether or not to expand a particular
intrinsic to the shuffevector sequence.

Differential Revision: https://reviews.llvm.org/D32245

llvm-svn: 302631
2017-05-10 09:42:49 +00:00
Craig Topper a584af5c8e [APInt] Fix indentation of tcDivide. Combine variable declaration and initialization.
llvm-svn: 302626
2017-05-10 07:50:17 +00:00
Craig Topper 62de039bd1 [APInt] Use getNumWords function in udiv/urem/udivrem instead of reimplementinging it.
llvm-svn: 302625
2017-05-10 07:50:15 +00:00
Igor Breger fda31e64e0 [GlobalISel][X86] G_ZEXT i1 to i32/i64 support.
Summary: Support G_ZEXT i1 to i32/i64 instruction selection.

Reviewers: zvi, guyblank

Reviewed By: guyblank

Subscribers: rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D32965

llvm-svn: 302623
2017-05-10 06:52:58 +00:00
Mikael Holmen af14a21e50 [UnreachableBlockElim] Check return value of constrainRegClass().
Summary:
MachineRegisterInfo::constrainRegClass() can fail if two register classes
don't have a common subclass or if the register class doesn't contain
enough registers. Check the return value before trying to remove Phi nodes,
and if we can't constrain, we output a COPY instead of simply replacing
registers.

Reviewers: kparzysz, david2050, wmi

Reviewed By: kparzysz

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32999

llvm-svn: 302622
2017-05-10 06:33:43 +00:00