Commit Graph

109405 Commits

Author SHA1 Message Date
NAKAMURA Takumi 61b2f48453 llvm/test/Transforms/GCOVProfiling: Avoid to parse backslashes in MDString. Use %/T instead of %T.
LLVM Parser decodes "\bb" as hex in "C:\bb-win7\buildername\build...", with MDString.

See also, http://llvm.org/docs/LangRef.html#metadata-nodes-and-metadata-strings

This reverts r221270, "Disable 3 tests in llvm/test/Transforms/GCOVProfiling/ for now. Investigating."

FIXME: Please check EC in GCOVProfiler::emitProfileNotes().
llvm-svn: 221334
2014-11-05 06:29:05 +00:00
David Majnemer 5026722287 llvm-readobj: Add support for dumping the DOS header in PE files
llvm-svn: 221333
2014-11-05 06:24:35 +00:00
Jiangning Liu 1fb71bc395 Revert 220932.
Commit 220932 caused crash when building clang-tblgen on aarch64 debian target,
so it's blocking all daily tests.

The std::call_once implementation in pthread has bug for aarch64 debian.

llvm-svn: 221331
2014-11-05 04:44:31 +00:00
Duncan P. N. Exon Smith b28deb1967 IR: Metadata: Remove unnecessary dyn_cast
llvm-svn: 221328
2014-11-05 01:55:06 +00:00
Matt Arsenault 5d85d57f65 Fix broken C++ mode comment
llvm-svn: 221327
2014-11-05 01:36:22 +00:00
David Majnemer bf7550e7ec InstSimplify: Exact shifts of X by Y are X if X has the lsb set
Exact shifts may not shift out any non-zero bits. Use computeKnownBits
to determine when this occurs and just return the left hand side.

This fixes PR21477.

llvm-svn: 221325
2014-11-05 00:59:59 +00:00
Eric Christopher 65ec83b09f Add a check for misbehaving -Wcomment from gcc-4.7 and add
-Wno-comment to the compilation flags if so.

Patch by Filipe Cabecinhas, configure regenerated by me.

llvm-svn: 221323
2014-11-05 00:35:15 +00:00
Tim Northover dc0d9e46a5 ARM: try to add extra CS-register whenever stack alignment >= 8.
We currently try to push an even number of registers to preserve 8-byte
alignment during a function's prologue, but only when the stack alignment is
prcisely 8. Many of the reasons for doing it apply also when that alignment > 8
(the extra store is often free, and can save another stack adjustment, though
less frequently for 16-byte stack alignment).

llvm-svn: 221321
2014-11-05 00:27:20 +00:00
Tim Northover 228c943f31 ARM/Dwarf: correctly align stack before callee-saved VPRs
We were making an attempt to do this by adding an extra callee-saved GPR (so
that there was an even number in the list), but when that failed we went ahead
and pushed anyway.

This had a couple of potential issues:
  + The .cfi directives we emit misplaced dN because they were based on
    PrologEpilogInserter's calculation.
  + Unaligned stores can be less efficient.
  + Unaligned stores can actually fault (likely only an issue in niche cases,
    but possible).

This adds a final explicit stack adjustment if all other options fail, so that
the actual locations of the registers match up with where they should be.

llvm-svn: 221320
2014-11-05 00:27:13 +00:00
David Majnemer f20d7c4c61 Analysis: Make isSafeToSpeculativelyExecute fire less for divides
Divides and remainder operations do not behave like other operations
when they are given poison: they turn into undefined behavior.

It's really hard to know if the operands going into a div are or are not
poison.  Because of this, we should only choose to speculate if there
are constant operands which we can easily reason about.

This fixes PR21412.

llvm-svn: 221318
2014-11-04 23:49:08 +00:00
Reid Kleckner 941e93e9a8 Revert "[Reassociate] Canonicalize negative constants out of expressions."
This reverts commit r221171.

It performs this invalid transformation:
-  %div.i = urem i64 -1, %add
-  %sub.i = sub i64 -2, %div.i
+  %div.i = urem i64 1, %add
+  %sub.i1 = add i64 %div.i, -2

llvm-svn: 221317
2014-11-04 23:42:45 +00:00
Simon Pilgrim c9a0779309 [X86][SSE] Enable commutation for SSE immediate blend instructions
Patch to allow (v)blendps, (v)blendpd, (v)pblendw and vpblendd instructions to be commuted - swaps the src registers and inverts the blend mask.

This is primarily to improve memory folding (see new tests), but it also improves the quality of shuffles (see modified tests).

Differential Revision: http://reviews.llvm.org/D6015

llvm-svn: 221313
2014-11-04 23:25:08 +00:00
Mark Heffernan 2d393ea6ef Revert earlier change removing setPreservesCFG from instcombine (r221223) and
change LoopSimplifyPass to be !isCFGOnly.  The motivation for the earlier patch
(r221223) was that LoopSimplify is not preserved by instcombine though
setPreservesCFG indicates that it is.  This change fixes the issue
by making setPreservesCFG no longer imply LoopSimplifyPass, and is therefore less
invasive.

llvm-svn: 221311
2014-11-04 23:02:09 +00:00
Juergen Ributzka f9660f0712 [AArch64] Use the correct register class for ORR.
While fixing up the register classes in the machine combiner in a previous
commit I missed one.

This fixes the last one and adds a test case.

llvm-svn: 221308
2014-11-04 22:20:07 +00:00
Rafael Espindola d85260827c Revert "[mips] Add names and tests for the hardware registers"
This reverts commit r221299.

The tests

    LLVM :: MC/Disassembler/Mips/mips32.txt
    LLVM :: MC/Disassembler/Mips/mips32_le.txt

were failing.

llvm-svn: 221307
2014-11-04 22:15:05 +00:00
David Blaikie 3a443c29b9 Provide gmlt-like inline scope information in the skeleton CU to facilitate symbolication without needing the .dwo files
Clang -gsplit-dwarf self-host -O0, binary increases by 0.0005%, -O2,
binary increases by 25%.

A large binary inside Google, split-dwarf, -O0, and other internal flags
(GDB index, etc) increases by 1.8%, optimized build is 35%.

The size impact may be somewhat greater in .o files (I haven't measured
that much - since the linked executable -O0 numbers seemed low enough)
due to relocations. These relocations could be removed if we taught the
llvm-symbolizer to handle indexed addressing in the .o file (GDB can't
cope with this just yet, but GDB won't be reading this info anyway).
Also debug_ranges could be shared between .o and .dwo, though ideally
debug_ranges would get a schema that could used index(+offset)
addressing, and move to the .dwo file, then we'd be back to sharing
addresses in the address pool again.

But for now, these sizes seem small enough to go ahead with this.

Verified that no other DW_TAGs are produced into the .o file other than
subprograms and inlined_subroutines.

llvm-svn: 221306
2014-11-04 22:12:25 +00:00
David Blaikie 9bfd7a9f43 Move cross-unit DIE caching to the DwarfFile level, so it doesn't interfere with fission-gmlt data and produce skeleton<>full unit cross referencing.
llvm-svn: 221305
2014-11-04 22:12:18 +00:00
Rafael Espindola bfd0f01dd7 Don't produce relocations for a difference in a section with no symbols.
We were producing a relocation for
----------------
.section foo,bar
La:
Lb:
 .long   La-Lb
--------------

but not for

---------------------
  .section foo,bar
zed:
La:
Lb:
 .long   La-Lb
----------------

This patch handles the case where both fragments are part of the first atom
in a section and there is no corresponding symbol to that atom.

This fixes pr21328.

llvm-svn: 221304
2014-11-04 22:10:33 +00:00
Vasileios Kalintiris a16974a5c0 [mips] Move COP2 & COP3 load/store instructions from MipsInstrFPU.td to MipsInstrInfo.td. NFC.
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5843

llvm-svn: 221300
2014-11-04 21:45:16 +00:00
Vasileios Kalintiris df6e0d0371 [mips] Add names and tests for the hardware registers
Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5763

llvm-svn: 221299
2014-11-04 21:30:44 +00:00
Andrea Di Biagio f5b34e535d [X86] Add 'FeatureSlowSHLD' to cpu 'bdver3'. Also explicit set FeatureAVX and FeatureSSE4A for all the bdver* cpus.
This patch adds 'FeatureSlowSHLD' to 'bdver3'.
According to the official AMD optimization guide for amdfam15: "Using
alternative code in place of SHLD achieves lower overall latency and
requires fewer execution resources. The 32-bit and 64-bit forms of
ADD, ADC, SHR, and LEA (except 16-bit form) are DirectPath
instructions, while SHLD is a VectorPath instruction."

This patch also explicitly sets feature AVX and SSE4A for all the bdver*
cpus. This part of the patch is a non-functional change and it is mainly
done for clarity reasons (Both XOP and FMA4 already imply AVX and SSE4A).

llvm-svn: 221296
2014-11-04 21:18:09 +00:00
Justin Bogner af20fae2fb ErrorOr: Be more explicit in the implicit conversion to bool docs
llvm-svn: 221295
2014-11-04 21:01:48 +00:00
Arnaud A. de Grandmaison a11cab3120 [PBQP] Callee saved regs should have a higher cost than scratch regs
Registers are not all equal. Some are not allocatable (infinite cost),
some have to be preserved but can be used, and some others are just free
to use.

Ensure there is a cost hierarchy reflecting this fact, so that the
allocator will favor scratch registers over callee-saved registers.

llvm-svn: 221293
2014-11-04 20:51:29 +00:00
Arnaud A. de Grandmaison 829dd81377 [PBQP] Tweak spill costs and coalescing benefits
This patch improves how the different costs (register, interference, spill
and coalescing) relates together. The assumption is now that:
 - coalescing (or any other "side effect" of reg alloc) is negative, and
   instead of being derived from a spill cost, they use the block
   frequency info.
 - spill costs are in the [MinSpillCost:+inf( range
 - register or interference costs are in [0.0:MinSpillCost( or +inf

The current MinSpillCost is set to 10.0, which is a random value high
enough that the current constraint builders do not need to worry about
when settings costs. It would however be worth adding a normalization
step for register and interference costs as the last step in the
constraint builder chain to ensure they are not greater than SpillMinCost
(unless this has some sense for some architectures). This would work well
with the current builder pipeline, where all costs are tweaked relatively
to each others, but could grow above MinSpillCost if the pipeline is
deep enough.

The current heuristic is tuned to depend rather on the number of uses of
a live interval rather than a density of uses, as used by the greedy
allocator. This heuristic provides a few percent improvement on a number
of benchmarks (eembc, spec, ...) and will definitely need to change once
spill placement is implemented: the current spill placement is really
ineficient, so making the cost proportionnal to the number of use is a
clear win.

llvm-svn: 221292
2014-11-04 20:51:24 +00:00
Matt Arsenault a95f5a0ec1 R600/SI: Rename div_scale dest operands to match documentation
llvm-svn: 221291
2014-11-04 20:29:20 +00:00
Benjamin Kramer 185dc0da1f AArch64: Pattern match integer vector abs like we do on ARM.
This kind of pattern is emitted by the loop vectorizer.

llvm-svn: 221289
2014-11-04 20:10:06 +00:00
Kostya Serebryany c5bd9810cc [asan] [mips] changed ShadowOffset32 for systems having 16kb PageSize; patch by Kumar Sukhani
llvm-svn: 221288
2014-11-04 19:46:15 +00:00
Rafael Espindola 649f172c17 Remove unused DisableRedZone option.
Patch by Steve King.

llvm-svn: 221282
2014-11-04 18:18:52 +00:00
David Majnemer 2de97fcd9a InstSimplify: Fold a hasNoSignedWrap() call into a match() expression
No functionality change intended, it's just a little more concise.

llvm-svn: 221281
2014-11-04 17:47:13 +00:00
David Majnemer 4f438377fb InstSimplify: Fold a hasNoUnsignedWrap() call into a match() expression
No functionality change intended, it's just a little more concise.

llvm-svn: 221280
2014-11-04 17:38:50 +00:00
Toma Tabacu cc2502d8f3 [mips] Improve support for the .set mips16/nomips16 assembler directives.
Summary:
Appropriately set/clear the FeatureBit for Mips16 when these assembler directives are used and also emit ".set nomips16" (previously, only ".set mips16" was being emitted).

These improvements allow for better testing of the .cpload/.cprestore assembler directives (which are not supposed to work when Mips16 is enabled).

Test Plan: The test is bare-bones because there are no MC tests for Mips16 instructions (there's only one, which checks that the Mips16 ELF header flag gets set), and that suggests to me that it has not been implemented yet in the IAS.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5462

llvm-svn: 221277
2014-11-04 17:18:07 +00:00
Juergen Ributzka 7d434ce7e5 [Stackmaps] Make test less fragile. NFC.
llvm-svn: 221276
2014-11-04 17:11:00 +00:00
Sanjay Patel aee8421088 remove function names from comments; NFC
llvm-svn: 221274
2014-11-04 16:27:42 +00:00
Sanjay Patel 547e9752ff fix typo in comment
llvm-svn: 221273
2014-11-04 16:09:50 +00:00
NAKAMURA Takumi 14e3fc6ad4 Disable 3 tests in llvm/test/Transforms/GCOVProfiling/ for now. Investigating.
llvm-svn: 221270
2014-11-04 14:41:53 +00:00
NAKAMURA Takumi 06ac98299f Remove "REQUIRES:shell" from tests. They work for me.
llvm-svn: 221269
2014-11-04 13:41:33 +00:00
Simon Atanasyan d2bfd00e71 [yaml2obj] Allow yaml2obj tool to recognize EF_MIPS_NAN2008 flag
llvm-svn: 221268
2014-11-04 13:33:36 +00:00
NAKAMURA Takumi f4de174a44 Re-enable tests in llvm/test/Object, corresponding to line_iterator's
change in r221153.

llvm-svn: 221265
2014-11-04 13:19:29 +00:00
NAKAMURA Takumi 217ee5bf92 llvm/test/Transforms/GCOVProfiling/linezero.ll: Use %/T instead of %T in regex. This works on win32.
llvm-svn: 221262
2014-11-04 13:00:48 +00:00
Rafael Espindola c1f30877e0 Remove FindProgramByName. NFC.
llvm-svn: 221258
2014-11-04 12:35:47 +00:00
Yaron Keren ec69a4ece1 Fix Visual C++ warning, Program.inc(85): warning C4018: '<' : signed/unsigned mismatch.
llvm-svn: 221252
2014-11-04 09:22:41 +00:00
Charlie Turner 34ec84ec7f Add missing tests for build attribute encodings in object files.
test/MC/ARM/directive-eabi_attribute.s was missing several tests of object file
encodings relative to the existing tests for assembly file encodings. This
commit adds the missing tests.

Change-Id: Ie110ca02b65e8f4d4c77f437bd09d03607fa5c0d
llvm-svn: 221250
2014-11-04 09:07:40 +00:00
David Majnemer ea9b8ee43d llvm-objdump: Pass DiceTableEntry by reference
DiceTableEntry is 24 bytes on my machine, it's probably better to pass
them by reference.

This fixes PR21464.

llvm-svn: 221247
2014-11-04 08:41:48 +00:00
NAKAMURA Takumi 72e626e305 sys::findProgramByName(): [Win32] Tweak to pass lowercase .exe to SearchPath() to appease clang Driver's tests.
It seems SearchPath() doesn't show actual extension on the filesystem.

FIXME: Shall we use FindFirstFile() here?
llvm-svn: 221246
2014-11-04 08:17:15 +00:00
David Majnemer b925715c56 CodeGen: Enable DWARF emission for MS ABI targets
This is experimental, just barely enough to get things to not
immediately combust.

A note for those who are curious:
Only lld can successfully link the object files, other linkers truncate
the section names making the debug sections illegible to debuggers.

Even with this in mind, we believe we are having trouble with SECREL
relocations.

llvm-svn: 221245
2014-11-04 08:03:31 +00:00
Yaron Keren 6091fe7db9 #include <winbase.h> is not enough for Visual C++ 2013, it errors:
1>C:\Program Files (x86)\Windows Kits\8.1\Include\um\minwinbase.h(46):
error C2146: syntax error : missing ';' before identifier 'nLength'
1>C:\Program Files (x86)\Windows Kits\8.1\Include\um\minwinbase.h(46):
error C4430: missing type specifier - int assumed. Note: C++ does not support default-int
...

including <windows.h> is actually required.

llvm-svn: 221244
2014-11-04 07:53:30 +00:00
David Majnemer 83d6857b72 test: Restore llvm-lit (at least for my machine)
r221137 feeds None into os.path.join which is not valid.

llvm-svn: 221242
2014-11-04 05:54:50 +00:00
David Majnemer d28edfea03 Minimize test case further
No functional change intended.

llvm-svn: 221237
2014-11-04 05:17:58 +00:00
NAKAMURA Takumi 8d8f396d86 R600/LLVMBuild.txt: Add TransformUtils.
llvm-svn: 221228
2014-11-04 02:16:53 +00:00
Tim Northover 43361440bd Docs: give binutils/gold instructions for CMake too.
Patch by Steve King.

llvm-svn: 221227
2014-11-04 02:16:03 +00:00