Commit Graph

7 Commits

Author SHA1 Message Date
Frank Derry Wanye 83af66e18e new altera ID dependent backward branch check
This lint check is a part of the FLOCL (FPGA Linters for OpenCL) project
out of the Synergy Lab at Virginia Tech.

FLOCL is a set of lint checks aimed at FPGA developers who write code
in OpenCL.

The altera ID dependent backward branch lint check finds ID dependent
variables and fields used within loops, and warns of their usage. Using
these variables in loops can lead to performance degradation.
2021-05-06 17:01:39 -04:00
Frank Derry Wanye 5a87f81fe9 new altera unroll loops check
This lint check is a part of the FLOCL (FPGA Linters for OpenCL)
project out of the Synergy Lab at Virginia Tech.

FLOCL is a set of lint checks aimed at FPGA developers who write code
in OpenCL.

The altera unroll loops check finds inner loops that have not been
unrolled, as well as fully-unrolled loops that should be partially
unrolled due to unknown loop bounds or a large number of loop
iterations.

Based on the Altera SDK for OpenCL: Best Practices Guide.
2021-03-22 13:09:53 -04:00
Frank Derry Wanye e69e551e0e new altera single work item barrier check
This lint check is a part of the FLOCL (FPGA Linters for OpenCL)
project out of the Synergy Lab at Virginia Tech.

FLOCL is a set of lint checks aimed at FPGA developers who write code
in OpenCL.

The altera single work item barrier check finds OpenCL kernel functions
that call a barrier function but do not call an ID function. These
kernel functions will be treated as single work-item kernels, which
could be inefficient or lead to errors.

Based on the "Altera SDK for OpenCL: Best Practices Guide."
2020-12-18 07:52:20 -05:00
Frank Derry Wanye 9ca6fc4e09 Add a new altera kernel name restriction check to clang-tidy.
The altera kernel name restriction check finds kernel files and include
directives whose filename is "kernel.cl", "Verilog.cl", or "VHDL.cl".
Such kernel file names cause the Altera Offline Compiler to generate
intermediate design files that have the same names as certain internal
files, which leads to a compilation error.

As per the "Guidelines for Naming the Kernel" section in the "Intel FPGA
SDK for OpenCL Pro Edition: Programming Guide."

This reverts the reversion from 43a38a6523.
2020-11-09 09:26:50 -05:00
Nico Weber c88390468c Revert "Add a new altera kernel name restriction check to clang-tidy."
This reverts commit 43a38a6523,
and follow-up 5a7bc5e259.

The commit breaks check-clang-tools, the test added in the change
does not pass.
2020-11-02 10:30:42 -05:00
Frank Derry Wanye 43a38a6523 Add a new altera kernel name restriction check to clang-tidy.
The altera kernel name restriction check finds kernel files and include
directives whose filename is "kernel.cl", "Verilog.cl", or "VHDL.cl".
Such kernel file names cause the Altera Offline Compiler to generate
intermediate design files that have the same names as certain internal
files, which leads to a compilation error.

As per the "Guidelines for Naming the Kernel" section in the "Intel FPGA
SDK for OpenCL Pro Edition: Programming Guide."
2020-11-02 10:11:38 -05:00
Frank Derry Wanye 156b127945 Add a new altera check for structure packing and alignment.
The altera struct pack align lint check finds structs that are inefficiently
packed or aligned and recommends packing/aligning of the structs using the
packed and aligned attributes as needed in a warning.
2020-09-08 09:35:14 -04:00