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7323 Commits

Author SHA1 Message Date
Rafael Espindola ff33241e16 call libc memcpy/memset if array size is bigger then threshold. 
Coping 100MB array (after a warmup) shows that glibc 2.6.1 implementation on
x86-64 (core 2) is 30% faster (from 0.270917s to 0.188079s)

llvm-svn: 41479
 2007-08-27 10:18:20 +00:00
Chris Lattner d8c9cb9182 rename isOperandValidForConstraint to LowerAsmOperandForConstraint, 
changing the interface to allow for future changes.

llvm-svn: 41384
 2007-08-25 00:47:38 +00:00
Chris Lattner a124f69c52 Disable EH generation until PPC works 100%. 
llvm-svn: 41360
 2007-08-24 16:00:15 +00:00
Chris Lattner 51883acec1 add a note 
llvm-svn: 41359
 2007-08-24 15:17:59 +00:00
Chris Lattner 33800d1428 add some notes on really poor codegen. 
llvm-svn: 41319
 2007-08-23 15:22:07 +00:00
Chris Lattner 92c6a65d4e new example 
llvm-svn: 41318
 2007-08-23 15:16:03 +00:00
Bill Wendling 862afea91e Add the PCSymbol for Darwin x86 platforms. 
llvm-svn: 41284
 2007-08-22 18:44:05 +00:00
Bruno Cardoso Lopes b10580ac1e InlineAsm asm support for integer registers added 
llvm-svn: 41225
 2007-08-21 16:09:25 +00:00
Bruno Cardoso Lopes d4b9945a21 Instruction Itinerary attribution fixed 
llvm-svn: 41224
 2007-08-21 16:06:45 +00:00
Anton Korobeynikov f335679b52 Use only 1 knob to enable exceptions on Darwin :). 
llvm-svn: 41208
 2007-08-21 00:31:30 +00:00
Rafael Espindola 9c3d20d823 Partial implementation of calling functions with byval arguments: 
*) The needed information is propagated to the DAG
 *) The X86-64 backend detects it and aborts

llvm-svn: 41179
 2007-08-20 15:18:24 +00:00
Chris Lattner 78846b69ae add a note 
llvm-svn: 41178
 2007-08-20 02:14:33 +00:00
Bruno Cardoso Lopes 9fbef51078 MipsHi now has ouput flag 
MipsAdd SDNode created to add support to an Add opcode which supports input flag
Added an instruction itinerary to all instruction classes
Added branches with zero cond codes
Now call clobbers all non-callee saved registers
Call w/ register support added
Added DelaySlot to branch and load instructions
Added patterns to handle all setcc, brcond/setcc and MipsAdd instructions

llvm-svn: 41161
 2007-08-18 02:37:46 +00:00
Bruno Cardoso Lopes eabe61b080 Fixed stack frame addressing bug 
llvm-svn: 41160
 2007-08-18 02:19:09 +00:00
Bruno Cardoso Lopes f3c55807f2 support for Schedule included on Mips.td 
llvm-svn: 41159
 2007-08-18 02:18:07 +00:00
Bruno Cardoso Lopes 4bd7f4db9f Removed LowerRETURADDR, fixed small bug into LowerRET, LowerGlobalAddress 
fixed to generate instructions (add, lui) glued!

llvm-svn: 41158
 2007-08-18 02:16:30 +00:00
Bruno Cardoso Lopes 833a1f9b55 Couple of small changes. Delay Slot handle header declared. 
Newline added after macros at function init on generated asm!

llvm-svn: 41157
 2007-08-18 02:05:24 +00:00
Bruno Cardoso Lopes 5792189590 Added InstrItinClass support for instruction formats 
llvm-svn: 41156
 2007-08-18 02:01:28 +00:00
Bruno Cardoso Lopes 0c530638c7 Branch Analysis and InsertNoop inserted into header files 
llvm-svn: 41155
 2007-08-18 01:59:45 +00:00
Bruno Cardoso Lopes a746512fc5 createMipsDelaySlotFillerPass added to mips codegen runtime 
llvm-svn: 41154
 2007-08-18 01:58:15 +00:00
Bruno Cardoso Lopes 7b616f5742 Added Branch Analysis support 
Added InsertNoop support

llvm-svn: 41153
 2007-08-18 01:56:48 +00:00
Bruno Cardoso Lopes e8d1c52cd4 LowerRETURNADDR removed since it was wrong and does not have utility yet! 
MipsAdd opcode added

llvm-svn: 41152
 2007-08-18 01:54:09 +00:00
Bruno Cardoso Lopes 87beec9afb InstrItineraryData support on added. 
Added Mips3 ISA feature (needed when supporting R4000 machines)

llvm-svn: 41151
 2007-08-18 01:52:27 +00:00
Bruno Cardoso Lopes 0b97ce752c A Pass to insert Nops on intructions with DelaySlot 
llvm-svn: 41150
 2007-08-18 01:50:47 +00:00
Bruno Cardoso Lopes 415ded5d5a Mips generic fallback instruction schedule support! 
llvm-svn: 41149
 2007-08-18 01:46:44 +00:00
Anton Korobeynikov 597c8b77e4 Move ReturnAddrIndex variable to X86MachineFunctionInfo structure. This fixed 
hard to catch bugs with retaddr lowering

llvm-svn: 41104
 2007-08-15 17:12:32 +00:00
Chris Lattner db8adb9941 add a note. 
llvm-svn: 41103
 2007-08-15 16:58:38 +00:00
Evan Cheng b2823dac69 Fix a typo pointd out by Maarten ter Huurne. 
llvm-svn: 41059
 2007-08-13 23:27:11 +00:00
Dan Gohman ccb3611881 When x86 addresses matching exceeds its recursion limit, check to 
see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.

llvm-svn: 41049
 2007-08-13 20:03:06 +00:00
Chris Lattner 4e7f673f65 Fix PR1607 
llvm-svn: 41048
 2007-08-13 18:42:37 +00:00
Chris Lattner 750b3dfcf5 expand a note 
llvm-svn: 41021
 2007-08-11 18:19:07 +00:00
Chris Lattner ee44ab5b5f With evan's explicit flag representation, hopefully we will finally be 
able to 3-addressify away stuff like this:

        movl    %ecx, %eax
        decl    %eax

llvm-svn: 41020
 2007-08-11 18:16:46 +00:00
Bill Wendling cdbd82ee37 64-bit SSSE3 ops that use MMX registers don't require 16-byte alignment. 
Make a 'memop' pattern just for them.

llvm-svn: 41017
 2007-08-11 09:52:53 +00:00
Christopher Lamb 44e79f8aba Use subregs to improve any_extend code generation when feasible. 
llvm-svn: 41013
 2007-08-10 22:22:41 +00:00
Christopher Lamb b372abab14 Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)). 
llvm-svn: 41010
 2007-08-10 21:48:46 +00:00
Christopher Lamb f0c236fb8a Edit README in light of previous LEA16 commit. 
llvm-svn: 41009
 2007-08-10 21:29:05 +00:00
Christopher Lamb d36d30b53c Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled. 
llvm-svn: 41007
 2007-08-10 21:18:25 +00:00
Rafael Espindola 66011c17d5 propagate struct size and alignment of byval arguments to the DAG 
llvm-svn: 40986
 2007-08-10 14:44:42 +00:00
Bill Wendling 7014615087 For kicks, I though it would be fun to use the correct opcode. 
llvm-svn: 40985
 2007-08-10 09:00:17 +00:00
Bill Wendling 2377206923 Adding SSSE3 intrinsics. 
llvm-svn: 40982
 2007-08-10 06:22:27 +00:00
Evan Cheng f855b626e8 Temporarily backing out this change until we know why some dejagnu tests are failing. 
llvm-svn: 40973
 2007-08-09 22:25:35 +00:00
Evan Cheng e32e923a6a divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead. 
llvm-svn: 40972
 2007-08-09 21:59:35 +00:00
Evan Cheng a05ec4dc52 GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_. 
llvm-svn: 40970
 2007-08-09 18:05:17 +00:00
Dale Johannesen ba1a98a4e0 long double 9 of N. This finishes up the X86-32 bits 
(constants are still not handled).  Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).

llvm-svn: 40958
 2007-08-09 01:04:01 +00:00
Dale Johannesen f5124b36e4 Fix arguments for some Altivec instructions. From SWB. 
llvm-svn: 40957
 2007-08-09 00:49:19 +00:00
Dale Johannesen 4e7ff3593c Fix spelling of mtvscr and mfvscr. 
llvm-svn: 40908
 2007-08-07 23:08:00 +00:00
Dale Johannesen a47f7d7cfd Long double patch 8 of N: make it partially work in 
SSE mode (all but conversions <-> other FP types, I think):
>>Do not mark all-80-bit operations as "Requires[FPStack]"
(which really means "not SSE").
>>Refactor load-and-extend to facilitate this.
>>Update comments.
>>Handle long double in SSE when computing FP_REG_KILL.

llvm-svn: 40906
 2007-08-07 20:29:26 +00:00
Evan Cheng f7c6effc44 Initial JIT support for ARM by Raul Fernandes Herbster. 
llvm-svn: 40887
 2007-08-07 01:37:15 +00:00
Dale Johannesen 57c6ac5fe5 Long double patch 7 of N, unless I lost count:). 
Last x87 bits for full functionality (not
thoroughly tested, and long doubles do not work
in SSE modes at all - use -mcpu=i486 for now)

llvm-svn: 40886
 2007-08-07 01:17:37 +00:00
Dale Johannesen a010822b45 Replace 4-line function with 10-line version per review comment. 
llvm-svn: 40881
 2007-08-06 22:10:35 +00:00