a54b9643aa
A new entry.
...
llvm-svn: 28848
2006-06-17 00:45:49 +00:00
49cadab385
Implement the getPointerRegClass method, which is required for the ptr_rc
...
magic to work.
llvm-svn: 28847
2006-06-17 00:01:04 +00:00
8dd21436db
Forgot operands were hard coded for compile unit.
...
llvm-svn: 28846
2006-06-16 23:36:12 +00:00
d2e9a67cd9
Later models likely to have Yonah like attributes.
...
llvm-svn: 28843
2006-06-16 21:58:49 +00:00
638ee4ee15
Upgrade some load/store instructions to use the proper addressing mode stuff.
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llvm-svn: 28841
2006-06-16 21:29:41 +00:00
e8fe5e2bf4
In 64-bit mode, addr mode operands use G8RC instead of GPRC.
...
llvm-svn: 28840
2006-06-16 21:29:03 +00:00
a5190ae7a9
fix some assumptions that pointers can only be 32-bits. With this, we can
...
now compile:
static unsigned long X;
void test1() {
X = 0;
}
into:
_test1:
lis r2, ha16(_X)
li r3, 0
stw r3, lo16(_X)(r2)
blr
Totally amazing :)
llvm-svn: 28839
2006-06-16 21:01:35 +00:00
b429983988
Split 64-bit instructions out into a separate .td file
...
llvm-svn: 28838
2006-06-16 20:22:01 +00:00
61d703183e
Force 64-bit register availability in 64-bit mode. For real.
...
llvm-svn: 28837
2006-06-16 20:05:06 +00:00
a7d9db2fa5
Remove the -darwin and -aix llc options, inferring darwinism and aixism from
...
the target triple & subtarget info. woo.
llvm-svn: 28835
2006-06-16 18:50:48 +00:00
8a417a2fde
Add missing casts. This fixed some regressions.
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llvm-svn: 28834
2006-06-16 18:37:15 +00:00
6c79005b0d
Simplify TargetData ctor call
...
llvm-svn: 28832
2006-06-16 18:24:38 +00:00
f3b5b92e58
Don't pass target name into TargetData anymore, it is never used or needed.
...
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.
llvm-svn: 28830
2006-06-16 18:22:52 +00:00
7f043b52ff
Remove ctor with each piece specifyable (which causes overload ambiguities),
...
add a new init method.
llvm-svn: 28828
2006-06-16 18:11:26 +00:00
e796266d58
Only count instructions as code size, not constant pools and other per-function stuff.
...
llvm-svn: 28827
2006-06-16 18:09:26 +00:00
91f228b291
Simplify interpreter construction.
...
llvm-svn: 28826
2006-06-16 18:08:38 +00:00
16682fff2b
Document the subtarget features better, make sure that 64-bit mode, 64-bit
...
support, and 64-bit register use are all consistent with each other.
Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently. This not makes ppc64 blow up on lots
of stuff :)
llvm-svn: 28825
2006-06-16 17:50:12 +00:00
a35f306740
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
...
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
llvm-svn: 28824
2006-06-16 17:34:12 +00:00
0686842037
Add a error message to cbu to match bu
...
llvm-svn: 28819
2006-06-16 14:43:36 +00:00
fbee2e56cf
move header
...
llvm-svn: 28818
2006-06-16 14:33:53 +00:00
b2ff2d481e
1. Revise vector debug support.
...
2. Update docs for vector debug support and new version control.
3. Simplify serialization of DebugDescInfo subclasses.
llvm-svn: 28816
2006-06-16 13:14:03 +00:00
1fc4025a9c
More libcall transformations:
...
printf("%s\n", str) -> puts(str)
printf("%c", c) -> putchar(c)
Also fixed fprintf(file, "%c", c) -> fputc(c, file)
llvm-svn: 28815
2006-06-16 08:36:35 +00:00
f2ea587aa2
Simplify fprintf(file, "%s", str) to fputs(str, file).
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llvm-svn: 28814
2006-06-16 04:52:30 +00:00
0c4aa14deb
First baby step towards ppc64 support. This adds a new -march=ppc64 backend
...
that is currently just like ppc32 :)
llvm-svn: 28813
2006-06-16 01:37:27 +00:00
44ab8aefa6
Fix Regression/Linker/2006-06-15-GlobalVarAnment.ll
...
llvm-svn: 28812
2006-06-16 01:24:04 +00:00
57e8e38a6f
Only print the stack trace if it was requested. Previously, any call into
...
the Signals module that registered the handlers would cause the stack trace
to be generated. Now, you must explicitly call PrintStackTraceOnErrorSignal
in order for that to happen.
llvm-svn: 28810
2006-06-16 00:00:57 +00:00
4ff6c1646f
Teach the local allocator to know that live-in values (e.g. arguments) are
...
live at function entry. This prevents it from using arg registers for other
purposes before the arguments are used.
llvm-svn: 28809
2006-06-15 22:21:53 +00:00
cb29586ce4
Add a note that Nate noticed.
...
llvm-svn: 28808
2006-06-15 21:33:31 +00:00
19f964e048
1. Support standard dwarf format (was bootstrapping in Apple format.)
...
2. Add vector support.
llvm-svn: 28807
2006-06-15 20:51:43 +00:00
3519b87758
Was pointed out that structure alignment and type alignment are not the same
...
thing. Doubles still need to be special cased.
llvm-svn: 28806
2006-06-15 19:37:14 +00:00
c482a9e31a
Implement Transforms/InstCombine/bswap.ll, turning common shift/and/or bswap
...
idioms into bswap intrinsics.
llvm-svn: 28803
2006-06-15 19:07:26 +00:00
dce07568f2
Alignment of globals has not been quite right. Needed to drop the pointer type
...
to get the alignment of the element type.
llvm-svn: 28799
2006-06-15 13:10:58 +00:00
66f0e09313
Vector extract / insert index operand should have ptr type.
...
llvm-svn: 28798
2006-06-15 08:19:05 +00:00
94bb93f8f7
Type of extract_element index operand should be iPTR.
...
llvm-svn: 28797
2006-06-15 08:18:06 +00:00
de7156f12c
Type of vector extract / insert index operand should be iPTR.
...
llvm-svn: 28796
2006-06-15 08:14:54 +00:00
ef9e07d3f0
Consistency. EXTRACT_ELEMENT index operand should have ptr type.
...
llvm-svn: 28795
2006-06-15 08:11:54 +00:00
df63179d95
Assert. Rather than silently stop printing.
...
llvm-svn: 28794
2006-06-15 08:10:56 +00:00
55772ccfd6
Instructions with variable operands (variable_ops) can have a number required
...
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
llvm-svn: 28791
2006-06-15 07:22:16 +00:00
c8734381ac
X86 call instructions can take variable number of operands. Parameters of
...
vector types are passed via XMM registers.
llvm-svn: 28789
2006-06-14 22:24:55 +00:00
37c1c44c14
add a note
...
llvm-svn: 28787
2006-06-14 21:26:18 +00:00
ca25486603
Add argument registers to the end of call operand list (partial fix).
...
llvm-svn: 28783
2006-06-14 18:17:40 +00:00
f0a7a1a117
Change versioning to per debug info descriptor (merged with tag.)
...
llvm-svn: 28782
2006-06-14 14:45:39 +00:00
f67bec0579
Place dwarf headers at earliest possible point. Well behaved when skipping
...
functions.
llvm-svn: 28781
2006-06-14 11:35:03 +00:00
0c4f5a655a
Fix Transforms/LoopUnswitch/2006-06-13-SingleEntryPHI.ll, a loop unswitch
...
bug exposed by the recent lcssa work.
llvm-svn: 28779
2006-06-14 04:46:17 +00:00
4e744af80c
When asked not to delete useless PHIs, really don't delete them, no matter how
...
redundant they are.
llvm-svn: 28777
2006-06-14 04:43:14 +00:00
e3abb14503
Use the PotDoms map to memoize 'dominating value' lookup. With this patch,
...
LCSSA is still the slowest pass when gccas'ing 252.eon, but now it only takes
39s instead of 289s. :)
llvm-svn: 28776
2006-06-14 01:13:57 +00:00
e714a5c549
Fix another instance where PHI nodes need special treatment.
...
llvm-svn: 28774
2006-06-13 20:50:09 +00:00
7e428625c9
Update isLCSSAForm to handle PHI nodes specially for live-out detection. This
...
is the same as the recent patch to LCSSA.cpp.
llvm-svn: 28773
2006-06-13 20:45:22 +00:00
7c69df968c
I am sure I had commited this workaround before. Perhaps soon I should sort it all out
...
llvm-svn: 28772
2006-06-13 20:34:47 +00:00
3f8ff0449a
Fix a bug that was causing major slowdowns in povray. This was due to LCSSA
...
not handling PHI nodes correctly when determining if a value was live-out.
This patch reduces the number of detected live-out variables in the testcase
from 6565 to 485.
llvm-svn: 28771
2006-06-13 19:37:18 +00:00
Evan Cheng