475c6dbef6
ARM assembly parsing and encoding for SSAT16 instruction.
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llvm-svn: 136006
2011-07-25 23:09:14 +00:00
9212bf275d
Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128
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This also fixes PR10452
llvm-svn: 136004
2011-07-25 23:05:32 +00:00
ec21941de0
Add remaining 256-bit vector bitcasts. This also fixes PR10451
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llvm-svn: 136003
2011-07-25 23:05:28 +00:00
123dff0f58
- Handle special scalar_to_vector case: splats. Using a native 128-bit
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shuffle before inserting on a 256-bit vector.
- Add AVX versions of movd/movq instructions
- Introduce a few COPY patterns to match insert_subvector instructions.
This turns a trivial insert_subvector instruction into a register copy,
coalescing the xmm into a ymm and avoid emiting on more instruction.
llvm-svn: 136002
2011-07-25 23:05:25 +00:00
276eb8debf
Reintroduce r135730, this is indeed the right approach, there is no
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native 256-bit vector instruction to do scalar_to_vector.
llvm-svn: 136001
2011-07-25 23:05:16 +00:00
c956033947
Add a note about efficient codegen for binary log.
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llvm-svn: 135996
2011-07-25 22:30:00 +00:00
3a9cbeed73
ARM assembly parsing and encoding for SSAT instruction.
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Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
llvm-svn: 135990
2011-07-25 22:20:28 +00:00
55c8a78716
Refactoring fail.
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llvm-svn: 135986
2011-07-25 22:16:37 +00:00
6099cf16e5
Move CBackend and CppBackend MC initialization to TargetInfo.
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llvm-svn: 135982
2011-07-25 21:44:12 +00:00
ea8c66fea5
Get rid of an incorrect optimization for shuffles with PALIGNR and simplify isPALIGNRMask.
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Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle.
llvm-svn: 135980
2011-07-25 21:36:45 +00:00
9eec764c15
Fix more MC layering violations.
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llvm-svn: 135979
2011-07-25 21:32:49 +00:00
21b42e2498
More MC layering violations.
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llvm-svn: 135978
2011-07-25 21:29:26 +00:00
e96fd5a4fe
Add LLVMAddTargetLibraryInfo to the C API.
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llvm-svn: 135975
2011-07-25 21:20:54 +00:00
61faa55b74
Separate MCInstPrinter registration from AsmPrinter registration.
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llvm-svn: 135974
2011-07-25 21:20:24 +00:00
3ddf6aa503
Simply ARM so_reg MIOperandInfo definitions.
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The shift immediate encoding, printing, etc. is handled directly by the
enclosing operand definition, so it should be a vanilla immediate, not a
nested complex operand (shift_imm).
llvm-svn: 135968
2011-07-25 21:04:58 +00:00
f60768a14e
Fix last bits of MC layer issues. llvm-mc doesn't need to initialize TargetMachine's anymore.
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llvm-svn: 135963
2011-07-25 20:53:02 +00:00
ac798e1533
ARM asm operand renaming. Make things a bit more explicit.
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llvm-svn: 135959
2011-07-25 20:49:51 +00:00
eeaab22166
More simple cleanup of ARM asm operand definitions.
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llvm-svn: 135958
2011-07-25 20:38:18 +00:00
f5bf19530b
Code clean up.
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llvm-svn: 135954
2011-07-25 20:18:48 +00:00
d2e165d48b
Refactor MBlaze target to separate MC routines from Target routines.
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llvm-svn: 135953
2011-07-25 20:18:18 +00:00
43ab71a9a8
Update the comment. This feature is available only on Darwin at the moment. Though it's not Darwin-specific.
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llvm-svn: 135951
2011-07-25 20:15:15 +00:00
2d6ef44d39
Make assembly parser method names more consistent.
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llvm-svn: 135950
2011-07-25 20:14:50 +00:00
47d4aaf8ad
Unbreak the build.
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llvm-svn: 135949
2011-07-25 20:13:36 +00:00
46d575acc6
Tidy up formatting.
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Remove some inititalizers that are the same as the default, move defs next to
their (singular) uses and generally simplify some formatting of asm operand
definitions.
llvm-svn: 135946
2011-07-25 20:06:30 +00:00
5ed9fe8037
Tidy up a bit.
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llvm-svn: 135945
2011-07-25 20:00:32 +00:00
20b31548e6
Missed a file.
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llvm-svn: 135943
2011-07-25 19:55:33 +00:00
61d4a20f0f
Refactor PPC target to separate MC routines from Target routines.
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llvm-svn: 135942
2011-07-25 19:53:23 +00:00
b25310095f
More refactoring.
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llvm-svn: 135939
2011-07-25 19:33:48 +00:00
7e763d86ba
Refactor X86 target to separate MC code from Target code.
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llvm-svn: 135930
2011-07-25 18:43:53 +00:00
2dc0005b3c
Changed disabled code into a flag.
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llvm-svn: 135924
2011-07-25 18:04:49 +00:00
1d10909cb7
Remove dead variable.
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llvm-svn: 135923
2011-07-25 18:01:27 +00:00
b97270d58a
After we've modified the prolog to save volatile registers, generate the compact
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unwind encoding for that function. This simply crawls through the prolog looking
for machine instrs marked as "frame setup". It can calculate from these what the
compact unwind should look like.
This is currently disabled because of needed linker support. But initial tests
look good.
llvm-svn: 135922
2011-07-25 18:00:28 +00:00
aaba17e89b
Set PPCII::MO_DARWIN_STUB only on MacOSX < 10.5.
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llvm-svn: 135866
2011-07-24 08:22:56 +00:00
287bc6bdf6
ARMMCTargetDesc.h: Fixup to add DataTypes.h, or uint32_t would be unavailable.
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llvm-svn: 135837
2011-07-23 01:16:22 +00:00
f2596bc62a
Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where they belong.
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llvm-svn: 135833
2011-07-23 00:45:41 +00:00
6376593ed1
createXXXMCCodeGenInfo should be static.
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llvm-svn: 135826
2011-07-23 00:01:04 +00:00
ad5f485957
Sink ARM mc routines into MCTargetDesc.
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llvm-svn: 135825
2011-07-23 00:00:19 +00:00
801e0a3fde
ARM SSAT instruction 5-bit immediate handling.
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The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.
llvm-svn: 135823
2011-07-22 23:16:18 +00:00
e7e1e163db
ARM assembly parsing and encoding updates.
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Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.
llvm-svn: 135817
2011-07-22 22:06:05 +00:00
8c886a40d2
Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,
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InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.
llvm-svn: 135812
2011-07-22 21:58:54 +00:00
a89039998d
Fix PR10422 by adding the necessary AVX UCOMISD memory versions to
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load folding logic
llvm-svn: 135801
2011-07-22 20:53:20 +00:00
8dfcc0bb92
ARM assembly parsing and encoding of SMLAL instruction.
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Fix parsing of carry-setting variant SMLALS and add tests.
llvm-svn: 135797
2011-07-22 20:18:21 +00:00
d7c8c35301
ARM encoding and assembly parsing of SMLAD{X} instructions.
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Fix encoding of destination register. Add tests.
llvm-svn: 135796
2011-07-22 20:11:20 +00:00
d23a324132
Add v8f32->v8i32 bitcast. Fixes PR10440
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llvm-svn: 135794
2011-07-22 19:51:02 +00:00
77242dd537
Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64
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too. Patch by Jeff Muizelaar.
llvm-svn: 135789
2011-07-22 18:56:05 +00:00
c535278cf1
Fix x86's XALUO lowering to return its replacement values instead
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of doing the RAUW calls for the overflow value itself. This makes
it more consistent with how the rest of LegalizeDAG works.
llvm-svn: 135788
2011-07-22 18:45:15 +00:00
3fa7ca84d9
Fix test failures caused by my so_reg refactoring.
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llvm-svn: 135785
2011-07-22 18:30:30 +00:00
d1f8bde10f
ARM assembly parsing and encoding for SMC instruction.
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llvm-svn: 135782
2011-07-22 18:13:31 +00:00
bc9d841878
Clean up a few more comments.
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These instruction definitions are for the assembler, too, not just the
disassembler.
llvm-svn: 135781
2011-07-22 18:06:01 +00:00
163eb27c1a
Tidy up.
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llvm-svn: 135779
2011-07-22 18:04:10 +00:00
Jim Grosbach