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21202 Commits

Author SHA1 Message Date
Chris Lattner fea33f7e64 Use new PPC-specific nodes to represent shifts which require the 6-bit 
amount handling that PPC provides.  These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits.  This fixes a miscompilation of crafty with
the new front-end.

llvm-svn: 24615
 2005-12-06 02:10:38 +00:00
Andrew Lenharth e788bbf6ef added instructions with inverted immediates 
llvm-svn: 24614
 2005-12-06 00:33:53 +00:00
Andrew Lenharth 08c4a775e6 yea, it helps to have your path set right when testing 
llvm-svn: 24613
 2005-12-05 23:41:45 +00:00
Andrew Lenharth 3c7c4d7508 These never trigger, but whatever 
llvm-svn: 24612
 2005-12-05 23:19:44 +00:00
Evan Cheng c0c190239d Remove unnecessary let hasCtrlDep=1 now it can be inferred. 
llvm-svn: 24611
 2005-12-05 23:09:43 +00:00
Evan Cheng 0fe76d1585 * Infer instruction property hasCtrlDep from pattern if it has one. 
* Fixed a bug related to hasCtrlDep property use.

llvm-svn: 24610
 2005-12-05 23:08:55 +00:00
Andrew Lenharth 5bfcd1e63a move this over to the dag 
llvm-svn: 24609
 2005-12-05 20:50:53 +00:00
Chris Lattner 077200737c getRawValue zero extens for unsigned values, use getsextvalue so that we 
know that small negative values fit into the immediate field of addressing
modes.

llvm-svn: 24608
 2005-12-05 18:23:57 +00:00
Andrew Lenharth 9410433966 fix constant pool loads 
llvm-svn: 24607
 2005-12-05 17:51:02 +00:00
Chris Lattner 3539778883 Fix the #1 code quality problem that I have seen on X86 (and it also affects 
PPC and other targets).  In a particular, consider code like this:

struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
   return a.x * b.x  +  a.y * b.y  +  a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
   Vector3 r;
   r.x = dot( a, b.a );
   r.y = dot( a, b.b );
   r.z = dot( a, b.c );
   return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
   for (int i = 0; i < n; i++)
      x[i] = mul( x[i], m );
}

we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them).  Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:

LBB3_1: ; no_exit.preheader
        li r2, 0
        addi r6, r3, 64        ;; 9 values live across the loop body!
        addi r7, r3, 56
        addi r8, r3, 48
        addi r9, r3, 40
        addi r10, r3, 32
        addi r11, r3, 24
        addi r12, r3, 16
        addi r30, r3, 8
LBB3_2: ; no_exit
        lfd f0, 0(r30)
        lfd f1, 8(r4)
        fmul f0, f1, f0
        lfd f2, 0(r3)        ;; no constant indices folded into the loads!
        lfd f3, 0(r4)
        lfd f4, 0(r10)
        lfd f5, 0(r6)
        lfd f6, 0(r7)
        lfd f7, 0(r8)
        lfd f8, 0(r9)
        lfd f9, 0(r11)
        lfd f10, 0(r12)
        lfd f11, 16(r4)
        fmadd f0, f3, f2, f0
        fmul f2, f1, f4
        fmadd f0, f11, f10, f0
        fmadd f2, f3, f9, f2
        fmul f1, f1, f6
        stfd f0, 0(r4)
        fmadd f0, f11, f8, f2
        fmadd f1, f3, f7, f1
        stfd f0, 8(r4)
        fmadd f0, f11, f5, f1
        addi r29, r4, 24
        stfd f0, 16(r4)
        addi r2, r2, 1
        cmpw cr0, r2, r5
        or r4, r29, r29
        bne cr0, LBB3_2 ; no_exit

uh, yuck.  With this patch, we now sink the constant offsets into the loop, producing
this code:

LBB3_1: ; no_exit.preheader
        li r2, 0
LBB3_2: ; no_exit
        lfd f0, 8(r3)
        lfd f1, 8(r4)
        fmul f0, f1, f0
        lfd f2, 0(r3)
        lfd f3, 0(r4)
        lfd f4, 32(r3)       ;; much nicer.
        lfd f5, 64(r3)
        lfd f6, 56(r3)
        lfd f7, 48(r3)
        lfd f8, 40(r3)
        lfd f9, 24(r3)
        lfd f10, 16(r3)
        lfd f11, 16(r4)
        fmadd f0, f3, f2, f0
        fmul f2, f1, f4
        fmadd f0, f11, f10, f0
        fmadd f2, f3, f9, f2
        fmul f1, f1, f6
        stfd f0, 0(r4)
        fmadd f0, f11, f8, f2
        fmadd f1, f3, f7, f1
        stfd f0, 8(r4)
        fmadd f0, f11, f5, f1
        addi r6, r4, 24
        stfd f0, 16(r4)
        addi r2, r2, 1
        cmpw cr0, r2, r5
        or r4, r6, r6
        bne cr0, LBB3_2 ; no_exit

This is much nicer as it reduces register pressure in the loop a lot.  On X86,
this takes the function from having 9 spilled registers to 2.  This should help
some spec programs on X86 (gzip?)

This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.

llvm-svn: 24606
 2005-12-05 07:10:48 +00:00
Chris Lattner 7d4d93c52c Add a flag to Module::getGlobalVariable to allow it to return vars with 
internal linkage.

Patch provided by Evan Jones, thanks!

llvm-svn: 24604
 2005-12-05 05:30:21 +00:00
Chris Lattner ca18d19210 attribute((used)) is now supported 
llvm-svn: 24603
 2005-12-05 05:23:06 +00:00
Chris Lattner 165998207e Wrap a long line, never internalize llvm.used. 
llvm-svn: 24602
 2005-12-05 05:07:38 +00:00
Chris Lattner b0e9741022 New testcase for PR660 
llvm-svn: 24601
 2005-12-05 04:48:12 +00:00
Chris Lattner 7b43664aa0 testcase for PR664 
llvm-svn: 24600
 2005-12-05 03:22:46 +00:00
Chris Lattner 3c0b8f577d Several things: 
1. Remove redundant type casts now that PR673 is implemented.
2. Implement the OUT*ir instructions correctly.  The port number really
   *is* a 16-bit value, but the patterns should only match if the number
   is 0-255.  Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
   i8, not an i16 as they were believed to be before.  This previous fib
   stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.

llvm-svn: 24599
 2005-12-05 02:40:25 +00:00
Chris Lattner 282c2af4d8 On some targets (e.g. X86), shift amounts are not the same as the value 
being shifted.  Don't assume they are.

llvm-svn: 24598
 2005-12-05 02:37:26 +00:00
Chris Lattner ba369ae8f1 Implement PR673: for explicit register references, use type information 
if available

llvm-svn: 24597
 2005-12-05 02:36:37 +00:00
Chris Lattner 3717b4c830 Add some methods 
llvm-svn: 24596
 2005-12-05 02:35:08 +00:00
Chris Lattner c54cddd25b Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted. 
llvm-svn: 24595
 2005-12-05 02:34:29 +00:00
Chris Lattner f3322af5c6 Add some explicit type casts so that tblgen knows the type of the shift 
amount, which is not necessarily the same as the type being shifted.

llvm-svn: 24594
 2005-12-05 02:34:05 +00:00
Chris Lattner d49489f01e Generate code to silence bogus GCC warnings. 
llvm-svn: 24593
 2005-12-05 00:48:51 +00:00
Chris Lattner efc86f5f7a The basic fneg cases are already autogen'd 
llvm-svn: 24592
 2005-12-04 19:04:38 +00:00
Chris Lattner f979794717 Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen 
improvements.

llvm-svn: 24591
 2005-12-04 19:01:59 +00:00
Chris Lattner fd857daa0d Finish moving uncond br over to .td file, remove from .cpp file. 
llvm-svn: 24590
 2005-12-04 18:48:01 +00:00
Chris Lattner d9d18aff6a Define BR in the .td file now that Evan made tblgen smarter. 
llvm-svn: 24589
 2005-12-04 18:42:54 +00:00
Evan Cheng 95cb763818 Added isel patterns for RET, JMP, and WRITEPORT. 
llvm-svn: 24588
 2005-12-04 08:19:43 +00:00
Evan Cheng f02bb9af8b * Commit the fix (by Chris) for a tblgen type inferencing bug. 
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.

llvm-svn: 24587
 2005-12-04 08:18:16 +00:00
Evan Cheng e8531381e2 * Added instruction property hasCtrlDep for those which r/w control-flow 
chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
  chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.

llvm-svn: 24586
 2005-12-04 08:13:17 +00:00
Chris Lattner 7e79292fef Fix PR672 another way which should be more robust 
llvm-svn: 24585
 2005-12-04 06:03:50 +00:00
Chris Lattner 394350dcca new testcase, for PR672 
llvm-svn: 24584
 2005-12-04 06:03:25 +00:00
Chris Lattner 8782b782cd dbg.stoppoint returns a value, don't forget to init it 
llvm-svn: 24583
 2005-12-03 18:50:48 +00:00
Chris Lattner 3339c6a1f6 expand testcase, which has been in my tree for a while now 
llvm-svn: 24582
 2005-12-03 18:26:41 +00:00
Chris Lattner 2820b8c855 Fix SimplifyCFG/2005-12-03-IncorrectPHIFold.ll 
llvm-svn: 24581
 2005-12-03 18:25:58 +00:00
Chris Lattner 2492b74330 new testcase, miscompiled by simplifycfg. This has been distilled from Ptrdist/bc 
llvm-svn: 24580
 2005-12-03 18:25:32 +00:00
Chris Lattner bd23d34be0 Fix a bug in the testcase 
llvm-svn: 24579
 2005-12-03 17:20:57 +00:00
Chris Lattner ecfc7e56c5 Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672. 
This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on.  Given a clean nightly tester run, we should be able to turn it
on by default!

llvm-svn: 24578
 2005-12-03 07:15:55 +00:00
Chris Lattner 5d7a0a3aee new testcase for PR672 
llvm-svn: 24577
 2005-12-03 07:14:47 +00:00
Chris Lattner 352630141c Revert my previous patch which broke due to lazy streaming of functions 
from .bc files.

llvm-svn: 24575
 2005-12-02 19:00:22 +00:00
Andrew Lenharth f9b27d7011 bah, must generate all results 
llvm-svn: 24574
 2005-12-02 06:08:08 +00:00
Andrew Lenharth 73420b3795 cycle counter fix 
llvm-svn: 24573
 2005-12-02 04:56:24 +00:00
Chris Lattner 986cb40953 add a note 
llvm-svn: 24572
 2005-12-02 00:11:20 +00:00
Chris Lattner 0142afd6c1 Don't remove two operand, two result nodes from the binary ops map. These 
should come from the arbitrary ops map.

This fixes Regression/CodeGen/PowerPC/2005-12-01-Crash.ll

llvm-svn: 24571
 2005-12-01 23:14:50 +00:00
Chris Lattner e4ffb9a57d New testcase that crashes llc 
llvm-svn: 24570
 2005-12-01 23:14:09 +00:00
Chris Lattner ef2d8ca0b6 If a module has a main, but it is defined externally, refuse to run it. 
Attempting to run it will find lli's main, which isn't the desired effect.

llvm-svn: 24569
 2005-12-01 22:48:23 +00:00
Chris Lattner 05b0b4575b Promote line and column number information for our friendly 64-bit targets. 
llvm-svn: 24568
 2005-12-01 18:21:35 +00:00
Chris Lattner 93feffb4ed IA64 doesn't support the LOCATION node, and for some reason the ISelPattern 
stuff isn't using ISelLowering.cpp

llvm-svn: 24567
 2005-12-01 18:19:53 +00:00
Chris Lattner df9287836e Make sure these get added into the codegenmap when appropriate 
llvm-svn: 24566
 2005-12-01 18:09:22 +00:00
Chris Lattner 9d0d715e83 This is a bugfix for SelectNodeTo. In certain situations, we could be 
selecting a node and use a mix of getTargetNode() and SelectNodeTo.  Because
SelectNodeTo didn't check the CSE maps for a preexisting node and didn't insert
its result into the CSE maps, we would sometimes miss a CSE opportunity.

This is extremely rare, but worth fixing for completeness.

llvm-svn: 24565
 2005-12-01 18:00:57 +00:00
Andrew Lenharth 7bb09912c8 major think-o 
llvm-svn: 24564
 2005-12-01 17:48:51 +00:00