Commit Graph

367414 Commits

Author SHA1 Message Date
John Demme 76419525fb Common code preparation for tblgen-types patch
Cleanup and add methods which https://reviews.llvm.org/D86904 requires. Breaking up to lower review load.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D88267
2020-09-26 02:47:48 +00:00
Shilei Tian ebb1092a28 [Clang][OpenMP] Added support for nowait target in CodeGen via regular task
Previously for nowait target, CG emitted a function call to `__tgt_target_nowait`, etc. However, in OpenMP RTL, these functions just directly call the no-nowait version, which means nowait is not working as expected.

OpenMP specification says a target is acutally a target task, which is an untied and detachable task. It is natural to go to the direction that generates a task for a nowait target. However, OpenMP task has a problem that it must be within to a parallel region; otherwise the task will be executed immediately. As a result, if we directly wrap to a regular task, the `target nowait` outside of a parallel region is still a synchronous version.

In D77609, I added the support for unshackled task in OpenMP RTL. Basically, unshackled task is a task that is not bound to any parallel region. So all nowait target will be tranformed into an unshackled task. In order to distinguish from regular task, a new flag bit is set for unshackled task. This flag will be used by RTL for later process.

Since all target tasks are allocated via `__kmpc_omp_target_task_alloc`, and in current `libomptarget`, `__kmpc_omp_target_task_alloc` just calls `__kmpc_omp_task_alloc`. Therefore, we can modify the flag in `__kmpc_omp_target_task_alloc` so that we don't need to modify the FE too much. If users choose to opt out the feature, they just need to use a RTL w/o support of unshackled threads.

As a result, in this patch, the `target nowait` region is simply wrapped into a regular task. Later once we have RTL support for unshackled tasks, the wrapped tasks can be executed by unshackled threads w/o changes in the FE.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D78075
2020-09-25 22:10:36 -04:00
Amara Emerson 546e460a00 [AArch64][GlobalISel] If a G_BUILD_VECTOR operands are all G_CONSTANT then assign to gpr bank.
Even if the type is s8/s16, assigning to gpr is preferable with constants because
worst case we can select via a constant pool load, and without cross-bank copies
to the FPR bank more patterns can be imported later.
2020-09-25 18:27:57 -07:00
Arthur Eubanks 83e3ea2cfc [LowerTypeTests][NewPM] Add constructor that uses command line flags
This matches the legacy PM pass by having one constructor use command
line flags, and the other use parameters to the pass.

This fixes all tests under Transforms/LowerTypeTests using NPM.

Reviewed By: ychen, pcc

Differential Revision: https://reviews.llvm.org/D87845
2020-09-25 17:39:59 -07:00
Amara Emerson 2dba5461be [AArch64][GlobalISel] Add a few more vector type combinations for shift selection. 2020-09-25 17:35:10 -07:00
Fangrui Song 67782a0f99 [lldb/bindings] Fix -Wformat after D88123 2020-09-25 17:33:12 -07:00
Evandro Menezes a000580a89 [RISCV] Update driver tests
Add the RISC-V Bullet core to the driver tests.
2020-09-25 18:36:53 -05:00
Michael Collison 764c1b7a4d [RISCV] Scheduler description for Bullet
Add the pipeline model for the RISC-V Bullet micro architecture.

Co-authored-by: Evandro Menezes <evandro.menezes@sifive.com>
2020-09-25 18:36:53 -05:00
Alexander Shaposhnikov 97702c3d92 [Object][MachO] Refine the interface of Slice
This patch performs a minor cleanup of the class Slice:
static methods and constructors which take a pointer but assume that
it's not null now take the argument by reference.
NFC.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D88320
2020-09-25 16:27:45 -07:00
Craig Topper b5f46534c4 [IR] Improve the description for Constant::isNormalFP to list all things that are not normal instead of just denormal. NFC 2020-09-25 16:26:46 -07:00
Evandro Menezes 0291c471aa [RISCV] Fix formatting (NFC) 2020-09-25 18:15:04 -05:00
Juneyoung Lee 8bd205bf1d [LangRef] Clarify the behavior of memory access instructions when pointers/sizes aren't well-defined
This is a patch to LangRef that clarifies the behavior of load/store/memset/memcpy/memmove when the pointers or sizes are not well-defined
as well.

MSan detects a case when e.g., only lower bits of address are garbage when `-msan-check-access-address` is enabled, and it does not directly conflict with this patch because a C program should not use a pointer with undef bits and reasonable optimizations do not convert a well-defined pointer into a pointer with undef bits.

This patch contains a definition of a well-defined value as well.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D87994
2020-09-26 08:13:27 +09:00
Craig Disselkoen 51cad041e0 C API: functions to get mask of a ShuffleVector
This commit fixes a regression (from LLVM 10 to LLVM 11 RC3) in the LLVM
C API.

Previously, commit 1ee6ec2bf removed the mask operand from the
ShuffleVector instruction, storing the mask data separately in the
instruction instead; this reduced the number of operands of
ShuffleVector from 3 to 2. AFAICT, this change unintentionally caused
a regression in the LLVM C API. Specifically, it is no longer possible
to get the mask of a ShuffleVector instruction through the C API. This
patch introduces new functions which together allow a C API user to get
the mask of a ShuffleVector instruction, restoring the functionality
which was previously available through LLVMGetOperand().

This patch also adds tests for this change to the llvm-c-test
executable, which involved adding support for InsertElement,
ExtractElement, and ShuffleVector itself (as well as constant vectors)
to echo.cpp. Previously, vector operations weren't tested at all in
echo.ll.

I also fixed some typos in comments and help-text nearby these changes,
which I happened to spot while developing this patch. Since the typo
fixes are technically unrelated other than being in the same files, I'm
happy to take them out if you'd rather they not be included in the patch.

Differential Revision: https://reviews.llvm.org/D88190
2020-09-25 16:01:05 -07:00
Layton Kifer 48961ba0de [TRE][NFC] Refactor Basic Block Processing
Simplify and improve readability.

Differential Revision: https://reviews.llvm.org/D82269
2020-09-25 16:01:05 -07:00
Eli Friedman 4600e21051 [AArch64][SVE] Drop "argmemonly" from gather/scatter with vector base.
The intrinsics don't have any pointer arguments, so "argmemonly" makes
optimizations think they don't write to memory at all.

Differential Revision: https://reviews.llvm.org/D88186
2020-09-25 16:01:05 -07:00
Jim Ingham b65966cff6 Add the ability to write target stop-hooks using the ScriptInterpreter.
Differential Revision: https://reviews.llvm.org/D88123
2020-09-25 15:44:55 -07:00
Saleem Abdulrasool 58cdbf518b Sema: add support for `__attribute__((__swift_private__))`
This attribute allows declarations to be restricted to the framework
itself, enabling Swift to remove the declarations when importing
libraries.  This is useful in the case that the functions can be
implemented in a more natural way for Swift.

This is based on the work of the original changes in
8afaf3aad2

Differential Revision: https://reviews.llvm.org/D87720
Reviewed By: Aaron Ballman
2020-09-25 22:33:53 +00:00
Vitaly Buka 152ff3772c [msan] Skip memcpy interceptor called by gethostname
No test as reproducer requires particular glibc build.

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D88284
2020-09-25 15:26:34 -07:00
Jason Molenda 1bec6eb3f5 Add support for firmware/standalone LC_NOTE "main bin spec" corefiles
When a Mach-O corefile has an LC_NOTE "main bin spec" for a
standalone binary / firmware, with only a UUID and no load
address, try to locate the binary and dSYM by UUID and if
found, load it at offset 0 for the user.

Add a test case that tests a firmware/standalone corefile
with both the "kern ver str" and "main bin spec" LC_NOTEs.

<rdar://problem/68193804>

Differential Revision: https://reviews.llvm.org/D88282
2020-09-25 15:19:22 -07:00
Marco Vanotti a83eb048cb [lsan] Add interceptor for pthread_detach.
This commit adds an interceptor for the pthread_detach function,
calling into ThreadRegistry::DetachThread, allowing for thread contexts
to be reused.

Without this change, programs may fail when they create more than 8K
threads.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=47389

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D88184
2020-09-25 14:22:45 -07:00
Andrew Litteken 69c6f6be07 Revert "[IRSim] Adding basic implementation of llvm-sim."
This reverts commit 15645d044b.
2020-09-25 16:18:48 -05:00
Simon Pilgrim 7fa464f33d Fix copy+paste typo in doxygen parameter name to fix Wdocumentation. NFCI. 2020-09-25 22:09:51 +01:00
Simon Pilgrim 9ff9c1d8ee [InstCombine] matchRotate - support (uniform) constant rotation amounts (PR46895)
This patch adds handling of rotation patterns with constant shift amounts - the next bit will be how we want to support non-uniform constant vectors.

Differential Revision: https://reviews.llvm.org/D87452
2020-09-25 22:03:10 +01:00
Simon Pilgrim 994ef4e7bb [InstCombine] Fix test name to match type. NFCI.
We're testing a <2 x i36> not <2 x i16>
2020-09-25 22:00:36 +01:00
Andrew Litteken 15645d044b [IRSim] Adding basic implementation of llvm-sim.
This is a similarity visualization tool that accepts a Module and
passes it to the IRSimilarityIdentifier.  The resulting SimilarityGroups
are output in a JSON file.

Tests are found in test/tools/llvm-sim and check for the file not found,
a bad module, and that the JSON is created correctly.

Reviewers: paquette, jroelofs

Differential Revision: https://reviews.llvm.org/D86974
2020-09-25 15:12:34 -05:00
Simon Pilgrim 2a0ca17f66 [InstCombine] collectBitParts - add fshl/fshr handling
Pulled from D87452, this is a fixed version of the collectBitParts fshl/fshr handling which as @nikic noticed wasn't checking for different providers or had correct bit ordering (which was hid by only testing shift amounts of bitwidth/2).

Differential Revision: https://reviews.llvm.org/D88292
2020-09-25 20:34:59 +01:00
Arthur Eubanks d3f6972abb [LoopReroll][NewPM] Port -loop-reroll to NPM
Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D87957
2020-09-25 12:09:06 -07:00
Adrian Prantl 137597d4f4 Add a verifier check that rejects non-distinct DISubprogram function
attachments. They would crash the backend, which expects all
DISubprograms that are not part of the type system to have a unit field.

Clang right before https://reviews.llvm.org/D79967 would generate this
kind of broken IR.

rdar://problem/69534688

Thanks to Fangrui for fixing an assembler test I had missed!

https://reviews.llvm.org/D88270
2020-09-25 12:04:46 -07:00
Jonas Devlieghere 6cd4a4cd02 [lldb] Pass reference instead of pointer in protected SBAddress methods.
Every call to the protected SBAddress constructor and the SetAddress
method takes the address of a valid object which means we might as well
pass it as a const reference instead of a pointer and drop the null
check.

Differential revision: https://reviews.llvm.org/D88249
2020-09-25 11:47:05 -07:00
Thomas Lively 89fe083c19 [WebAssembly] Check features before making SjLj vars thread-local
1c5a3c4d38 updated the variables inserted by Emscripten SjLj lowering to be
thread-local, depending on the CoalesceFeaturesAndStripAtomics pass to downgrade
them to normal globals if the target features did not support TLS. However, this
had the unintended side effect of preventing all non-TLS-supporting objects from
being linked into modules with shared memory, because stripping TLS marks an
object as thread-unsafe. This patch fixes the problem by only making the SjLj
lowering variables thread-local if the target machine supports TLS so that it
never introduces new usage of TLS that will be stripped. Since SjLj lowering
works on Modules instead of Functions, this required that the
WebAssemblyTargetMachine have its feature string updated to reflect the
coalesced features collected from all the functions so that a
WebAssemblySubtarget can be created without using any particular function.

Differential Revision: https://reviews.llvm.org/D88323
2020-09-25 11:45:16 -07:00
Daniel Paoliello d2166076b8 [Coroutine] Split PHI Nodes in `cleanuppad` blocks in a way that obeys EH pad rules
Issue Details:
In order to support coroutine splitting, any multi-value PHI node in a coroutine is split into multiple blocks with single-value PHI Nodes, which then allows a subsequent transform to generate `reload` instructions as required (i.e., to reload the value if required if the coroutine has been resumed). This causes issues with EH pads (`catchswitch` and `catchpad`) as all pads within a `catchswitch` must have the same unwind destination, but the coroutine splitting logic may modify them to each have a unique unwind destination if there is a PHI node in the unwind `cleanuppad` that is set from values in the `catchswitch` and `cleanuppad` blocks.

Fix Details:
During splitting, if such a PHI node is detected, then create a "dispatcher" `cleanuppad` as well as the blocks with single-value PHI Nodes: thus the "dispatcher" is the unwind destination and it will detect which predecessor called it and then branch to the appropriate single-value PHI node block, which will then branch back to the original `cleanuppad` block.

Reviewed By: GorNishanov, lxfind

Differential Revision: https://reviews.llvm.org/D88059
2020-09-25 11:30:38 -07:00
Jez Ng 2c2a749448 [lld-macho] Ignore a few more undocumented flags
Reviewed By: #lld-macho, compnerd

Differential Revision: https://reviews.llvm.org/D88268
2020-09-25 11:28:37 -07:00
Jez Ng 643ec67a64 [lld-macho] Always include custom syslibroot when running tests
This greatly reduces the amount of boilerplate in our tests.

Reviewed By: #lld-macho, compnerd

Differential Revision: https://reviews.llvm.org/D87960
2020-09-25 11:28:36 -07:00
Jez Ng 62a3f0c984 [lld-macho] Support absolute symbols
They operate like Defined symbols but with no associated InputSection.

Note that `ld64` seems to treat the weak definition flag like a no-op for
absolute symbols, so I have replicated that behavior.

Reviewed By: #lld-macho, smeenai

Differential Revision: https://reviews.llvm.org/D87909
2020-09-25 11:28:35 -07:00
Jez Ng c7c9776f77 [lld-macho] Allow the entry symbol to be dynamically bound
Apparently this is used in real programs. I've handled this by reusing
the logic we already have for branch (function call) relocations.

Reviewed By: #lld-macho, smeenai

Differential Revision: https://reviews.llvm.org/D87852
2020-09-25 11:28:33 -07:00
Jez Ng f23f512691 [lld-macho] Support -bundle
Not 100% sure but it appears that bundles are almost identical to
dylibs, aside from the fact that they do not contain `LC_ID_DYLIB`. ld64's code
seems to treat bundles and dylibs identically in most places.

Supporting bundles allows us to run e.g. XCTests, as all test suites are
compiled into bundles which get dynamically loaded by the `xctest` test runner.

Reviewed By: #lld-macho, smeenai

Differential Revision: https://reviews.llvm.org/D87856
2020-09-25 11:28:32 -07:00
Jez Ng e4e673e75a [lld-macho] Implement support for PIC
* Implement rebase opcodes. Rebase opcodes tell dyld where absolute
  addresses have been encoded in the binary. If the binary is not loaded
  at its preferred address, dyld has to rebase these addresses by adding
  an offset to them.
* Support `-pie` and use it to test rebase opcodes.

This is necessary for absolute address references in dylibs, bundles etc
to work.

Reviewed By: #lld-macho, gkm

Differential Revision: https://reviews.llvm.org/D87199
2020-09-25 11:28:31 -07:00
clementval 06104cb9f2 [NFC] Fix comment for DataOp 2020-09-25 14:27:43 -04:00
Sourabh Singh Tomar d2f1f53043 [flang][OpenMP] Place the insertion point to the start of the block
After skeleton of the `Parallel Op` is created set the insertion point to start of the block. So that later `CodeGen` can proceed.

Note: This patch reflects the work that can be upstreamed from PR(merged)
PR: https://github.com/flang-compiler/f18-llvm-project/pull/424

Reviewed By: schweitz, kiranchandramohan

Differential Revision: https://reviews.llvm.org/D88221
2020-09-25 23:56:41 +05:30
Matt Arsenault 55c4ff91bd OpaquePtr: Add type to sret attribute
Make the corresponding change that was made for byval in
b7141207a4. Like byval, this requires a
bulk update of the test IR tests to include the type before this can
be mandatory.
2020-09-25 14:07:30 -04:00
Florian Hahn 7d274aa9be [SCEV] Add support for `x != 0` to CollectCondition.
Add support for NE predicates with 0 constants. Those can be translated
to UMaxExpr(x, 1).
2020-09-25 18:58:55 +01:00
Florian Hahn 3a69ebf0ad [SCEV] Add another test using info from loop guards for BTC with NE. 2020-09-25 18:58:55 +01:00
Hans Wennborg 4f1897c6f0 Move PassBuilder::registerParseTopLevelPipelineCallback out-of-line
For some mysterious reason it doesn't build with clang-cl when compiled
as part of the includes in clang's CodeGenAction.cpp
(crbug.com/1132292).
2020-09-25 19:55:40 +02:00
Adrian Prantl 8055ae31f4 Revert "Add a verifier check that rejects non-distinct DISubprogram function"
This reverts commit e17f52d623.

while investigating bot breakage.
2020-09-25 10:52:19 -07:00
Matt Arsenault 6cb0d23f2e AArch64/GlobalISel: Narrow stack passed argument access size
This fixes a verifier error in the testcase from bug 47619.

The stack passed s3 value was widened to 4-bytes, and producing a
4-byte memory access with a < 1 byte result type. We need to either
widen the result type or narrow the access size. This copies the code
directly from the AMDGPU handling, which narrows the load size. I
don't like that every target has to handle this, but this is currently
broken on the 11 release branch and this is the simplest fix.

This reverts commit 42bfa7c63b.
2020-09-25 13:35:17 -04:00
Haruki Imai c1f8568031 [MLIR] Fix for updating function signature in normalizing memrefs
Normalizing memrefs failed when a caller of symbolic use in a function
can not be casted to `CallOp`. This patch avoids the failure by checking
the result of the casting. If the caller can not be casted to `CallOp`,
it is skipped.

Differential Revision: https://reviews.llvm.org/D87746
2020-09-25 22:56:56 +05:30
Fangrui Song 6caf3fb817 Fix Assembler/disubprogram.ll after e17f52d623 2020-09-25 10:26:35 -07:00
Baptiste Saleil 9b86b70094 [PowerPC] Add accumulator register class and instructions
This patch adds the xxmfacc, xxmtacc and xxsetaccz instructions to manipulate
accumulator registers. It also adds the ACC register class definition for the
accumulator registers.

Differential Revision: https://reviews.llvm.org/D84847
2020-09-25 12:25:13 -05:00
Fangrui Song 7d0556fc13 Fix DISubprogram-v4.ll after e17f52d623 2020-09-25 10:08:43 -07:00
Saleem Abdulrasool 76eb163259 Sema: remove unnecessary parameter for SwiftName handling (NFCI)
This code never actually did anything in the implementation.

`mergeDeclAttribute` is declared as `static`, and referenced exactly
once in the file: from `Sema::mergeDeclAttributes`.

`Sema::mergeDeclAttributes` sets `LocalAMK` to `AMK_None`.  If the
attribute is `DeprecatedAttr`, `UnavailableAttr`, or `AvailabilityAttr`
then the `LocalAMK` is updated.  However, because we are dealing with a
`SwiftNameDeclAttr` here, `LocalAMK` remains `AMK_None`.  This is then
passed to the function which will as a result pass the value of
`AMK_None == AMK_Override` aka `false`.  Simply propagate the value
through and erase the dead codepath.

Thanks to Aaron Ballman for flagging the use of the availability merge
kind here leading to this simplification!

Differential Revision: https://reviews.llvm.org/D88263
Reviewed By: Aaron Ballman
2020-09-25 17:01:06 +00:00