Commit Graph

62 Commits

Author SHA1 Message Date
Carey Williams 76fd58d0fe Revert "[ARM] Allocatable Global Register Variables for ARM"
This reverts commit 2d739f98d8.
2019-11-29 17:01:05 +00:00
Anna Welker 2d739f98d8 [ARM] Allocatable Global Register Variables for ARM
Provides support for using r6-r11 as globally scoped
      register variables. This requires a -ffixed-rN flag
      in order to reserve rN against general allocation.

      If for a given GRV declaration the corresponding flag
      is not found, or the the register in question is the
      target's FP, we fail with a diagnostic.

      Differential Revision: https://reviews.llvm.org/D68862
2019-11-18 10:07:37 +00:00
Andrew Paverd d157a9bc8b Add Windows Control Flow Guard checks (/guard:cf).
Summary:
A new function pass (Transforms/CFGuard/CFGuard.cpp) inserts CFGuard checks on
indirect function calls, using either the check mechanism (X86, ARM, AArch64) or
or the dispatch mechanism (X86-64). The check mechanism requires a new calling
convention for the supported targets. The dispatch mechanism adds the target as
an operand bundle, which is processed by SelectionDAG. Another pass
(CodeGen/CFGuardLongjmp.cpp) identifies and emits valid longjmp targets, as
required by /guard:cf. This feature is enabled using the `cfguard` CC1 option.

Reviewers: thakis, rnk, theraven, pcc

Subscribers: ychen, hans, metalcanine, dmajor, tomrittervg, alex, mehdi_amini, mgorny, javed.absar, kristof.beyls, hiraditya, steven_wu, dexonsmith, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D65761
2019-10-28 15:19:39 +00:00
Sylvestre Ledru 7009204bd2 Decrease the verbosity of the -ftime-trace option
And move the relevant information in the doc.

Summary:
Currently, building a large software like Firefox shows
'Use chrome://tracing or Speedscope App (https://www.speedscope.app) for flamegraph visualization'
for each file.

Reviewers: anton-afanasyev

Reviewed By: anton-afanasyev

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D68260

llvm-svn: 373308
2019-10-01 07:52:42 +00:00
Jan Korous 72b9049b43 [static analyzer] Remove --analyze-auto
Differential Revision: https://reviews.llvm.org/D67934

llvm-svn: 372680
2019-09-24 00:37:25 +00:00
Jonas Paulsson 81aa62addf [SystemZ] Add SystemZ as supporting target in help text for -mfentry.
=> "Insert calls to fentry at function entry (x86/SystemZ only)"

Review: Ulrich Weigand
llvm-svn: 372387
2019-09-20 13:13:50 +00:00
Erich Keane e30b71f9dc Fix -dA flag, it is not a preprocessor flag.
-dA was in the d_group, which is a preprocessor state dumping group.
However -dA is a debug flag to cause a verbose asm.  It was already
implemented to do the same thing as -fverbose-asm, so make it just be an
alias.

llvm-svn: 369926
2019-08-26 17:00:13 +00:00
Anton Afanasyev 4fdcabf259 [Support] Fix `-ftime-trace-granularity` option
Summary:
Move `-ftime-trace-granularity` option to frontend options. Without patch
this option is showed up in the help for any tool that links libSupport.

Reviewers: sammccall

Subscribers: hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D65202

llvm-svn: 366911
2019-07-24 14:55:40 +00:00
Petr Hosek 08cb342afa [Driver] -noprofilelib flag
This flag is analoguous to other flags like -nostdlib or -nolibc
and could be used to disable linking of profile runtime library.
This is useful in certain environments like kernel, where profile
instrumentation is still desirable, but we cannot use the standard
runtime library.

llvm-svn: 365808
2019-07-11 19:06:38 +00:00
Ziang Wan de94ac9357 print-supported-cpus quality of life patch.
Claim all input files so that clang does not give a warning. Add two
short-cut aliases: -mcpu=? and -mtune=?.

llvm-svn: 364362
2019-06-25 23:57:14 +00:00
Ziang Wan af857b93df Add --print-supported-cpus flag for clang.
This patch allows clang users to print out a list of supported CPU models using
clang [--target=<target triple>] --print-supported-cpus

Then, users can select the CPU model to compile to using
clang --target=<triple> -mcpu=<model> a.c

It is a handy feature to help cross compilation.

llvm-svn: 363464
2019-06-14 21:42:21 +00:00
Stanislav Mekhanoshin 8a8131a3f6 [AMDGPU] gfx1010 wave32 clang support
Differential Revision: https://reviews.llvm.org/D63209

llvm-svn: 363341
2019-06-13 23:47:59 +00:00
Pengfei Wang 3a29f7c99c [X86] Add ENQCMD instructions
For more details about these instructions, please refer to the latest
ISE document:
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference.

Patch by Tianqing Wang (tianqing)

Differential Revision: https://reviews.llvm.org/D62282

llvm-svn: 362685
2019-06-06 08:28:42 +00:00
Pengfei Wang cc3629d545 [X86] Add VP2INTERSECT instructions
Support intel AVX512 VP2INTERSECT instructions in clang

Patch by Xiang Zhang (xiangzhangllvm)

Differential Revision: https://reviews.llvm.org/D62367

llvm-svn: 362196
2019-05-31 06:09:35 +00:00
J. Ryan Stinnett d45eaf9405 [Docs] Modernize references to macOS
Summary:
This updates all places in documentation that refer to "Mac OS X", "OS X", etc.
to instead use the modern name "macOS" when no specific version number is
mentioned.

If a specific version is mentioned, this attempts to use the OS name at the time
of that version:

* Mac OS X for 10.0 - 10.7
* OS X for 10.8 - 10.11
* macOS for 10.12 - present

Reviewers: JDevlieghere

Subscribers: mgorny, christof, arphaman, cfe-commits, lldb-commits, libcxx-commits, llvm-commits

Tags: #clang, #lldb, #libc, #llvm

Differential Revision: https://reviews.llvm.org/D62654

llvm-svn: 362113
2019-05-30 16:46:22 +00:00
Stanislav Mekhanoshin 91792f1b93 [AMDGPU] gfx1010 clang target
Differential Revision: https://reviews.llvm.org/D61875

llvm-svn: 360634
2019-05-13 23:15:59 +00:00
Luo, Yuanke 844f662932 Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference

Patch by LiuTianle

Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon

Reviewed By: craig.topper

Subscribers: mgorny, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D60552

llvm-svn: 360018
2019-05-06 08:25:11 +00:00
Sylvestre Ledru 90f1dfb062 Fix some typos in the clang doc.
Fixed with:
$ codespell -w ClangFormatStyleOptions.rst Toolchain.rst LanguageExtensions.rst ClangCommandLineReference.rst

llvm-svn: 350192
2019-01-01 12:51:14 +00:00
Scott Linder de6beb02a5 Implement -frecord-command-line (-frecord-gcc-switches)
Implement options in clang to enable recording the driver command-line
in an ELF section.

Implement a new special named metadata, llvm.commandline, to support
frontends embedding their command-line options in IR/ASM/ELF.

This differs from the GCC implementation in some key ways:

* In GCC there is only one command-line possible per compilation-unit,
  in LLVM it mirrors llvm.ident and multiple are allowed.
* In GCC individual options are separated by NULL bytes, in LLVM entire
  command-lines are separated by NULL bytes. The advantage of the GCC
  approach is to clearly delineate options in the face of embedded
  spaces. The advantage of the LLVM approach is to support merging
  multiple command-lines unambiguously, while handling embedded spaces
  with escaping.

Differential Revision: https://reviews.llvm.org/D54487
Clang Differential Revision: https://reviews.llvm.org/D54489

llvm-svn: 349155
2018-12-14 15:38:15 +00:00
Vitaly Buka 8076c57fd2 [asan] Add clang flag -fsanitize-address-use-odr-indicator
Reviewers: eugenis, m.ostapenko, ygribov

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D55157

llvm-svn: 348327
2018-12-05 01:44:31 +00:00
Filipe Cabecinhas 0eb5008352 Change -fsanitize-address-poison-class-member-array-new-cookie to -fsanitize-address-poison-custom-array-cookie
Handle it in the driver and propagate it to cc1

Reviewers: rjmccall, kcc, rsmith

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D52615

llvm-svn: 346001
2018-11-02 17:29:04 +00:00
Krzysztof Parzyszek 57e6706e56 [Hexagon] Remove support for V4
llvm-svn: 344786
2018-10-19 15:36:45 +00:00
Tri Vo 28e7e60ea4 [AArch64] Support adding X[8-15,18] registers as CSRs.
Summary:
Making X[8-15,18] registers call-saved is used to support
CONFIG_ARM64_LSE_ATOMICS in Linux kernel.

Signed-off-by: Tri Vo <trong@android.com>

Reviewers: srhines, nickdesaulniers, javed.absar

Reviewed By: nickdesaulniers

Subscribers: kristof.beyls, jfb, cfe-commits

Differential Revision: https://reviews.llvm.org/D52399

llvm-svn: 342990
2018-09-25 16:48:40 +00:00
Tri Vo 6e8abbc8b9 [AArch64] Support reserving x1-7 registers.
Summary: Reserving registers x1-7 is used to support CONFIG_ARM64_LSE_ATOMICS in Linux kernel. This change adds support for reserving registers x1 through x7.

Reviewers: javed.absar, efriedma, nickdesaulniers, srhines, phosek

Reviewed By: nickdesaulniers

Subscribers: manojgupta, jfb, cfe-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D48581

llvm-svn: 342100
2018-09-12 23:45:04 +00:00
Vedant Kumar 368540f6ee [docs] Regenerate ClangCommandLineReference.rst
llvm-svn: 340559
2018-08-23 17:55:03 +00:00
Fangrui Song df81b97927 [docs] Correct -fvisibility-inlines-hidden description
llvm-svn: 337505
2018-07-19 22:45:41 +00:00
Manoj Gupta da08f6ac16 [clang]: Add support for "-fno-delete-null-pointer-checks"
Summary:
Support for this option is needed for building Linux kernel.
This is a very frequently requested feature by kernel developers.

More details : https://lkml.org/lkml/2018/4/4/601

GCC option description for -fdelete-null-pointer-checks:
This Assume that programs cannot safely dereference null pointers,
and that no code or data element resides at address zero.

-fno-delete-null-pointer-checks is the inverse of this implying that
null pointer dereferencing is not undefined.

This feature is implemented in as the function attribute
"null-pointer-is-valid"="true".
This CL only adds the attribute on the function.
It also strips "nonnull" attributes from function arguments but
keeps the related warnings unchanged.

Corresponding LLVM change rL336613 already updated the
optimizations to not treat null pointer dereferencing
as undefined if the attribute is present.

Reviewers: t.p.northover, efriedma, jyknight, chandlerc, rnk, srhines, void, george.burgess.iv

Reviewed By: jyknight

Subscribers: drinkcat, xbolva00, cfe-commits

Differential Revision: https://reviews.llvm.org/D47894

llvm-svn: 337433
2018-07-19 00:44:52 +00:00
Piotr Padlewski e368de364e Add -fforce-emit-vtables
Summary:
 In many cases we can't devirtualize
 because definition of vtable is not present. Most of the
 time it is caused by inline virtual function not beeing
 emitted. Forcing emitting of vtable adds a reference of these
 inline virtual functions.
 Note that GCC was always doing it.

Reviewers: rjmccall, rsmith, amharc, kuhar

Subscribers: llvm-commits, cfe-commits

Differential Revision: https://reviews.llvm.org/D47108

Co-authored-by: Krzysztof Pszeniczny <krzysztof.pszeniczny@gmail.com>
llvm-svn: 334600
2018-06-13 13:55:42 +00:00
Petr Hosek 7250908016 [AArch64] Support reserving x20 register
Register x20 is a callee-saved register which may be used for other
purposes in certain contexts, for example to hold special variables
within the kernel. This change adds support for reserving this register
both to frontend and backend to make this register usable for these
purposes.

Differential Revision: https://reviews.llvm.org/D46552

llvm-svn: 334531
2018-06-12 20:00:50 +00:00
Alexander Ivchenko 0fb8c877c4 This patch aims to match the changes introduced
in gcc by https://gcc.gnu.org/ml/gcc-cvs/2018-04/msg00534.html.
The -mibt feature flag is being removed, and the -fcf-protection
option now also defines a CET macro and causes errors when used
on non-X86 targets, while X86 targets no longer check for -mibt
and -mshstk to determine if -fcf-protection is supported. -mshstk
is now used only to determine availability of shadow stack intrinsics.

Comes with an LLVM patch (D46882).

Patch by mike.dvoretsky

Differential Revision: https://reviews.llvm.org/D46881

llvm-svn: 332704
2018-05-18 11:56:21 +00:00
Gabor Buella a51e0c2243 [X86] directstore and movdir64b intrinsics
Reviewers: spatel, craig.topper, RKSimon

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45984

llvm-svn: 331249
2018-05-01 10:05:42 +00:00
Craig Topper 42da9cb091 [Docs] Regenerate command line documentation.
llvm-svn: 330654
2018-04-23 21:41:06 +00:00
Jonas Hahnfeld 06039e8fc1 [docs] Regenerate command line reference
This will correctly sort some manually added entries which should
generally be avoided!

llvm-svn: 330430
2018-04-20 13:26:03 +00:00
Gabor Buella a052016ef2 [x86] wbnoinvd intrinsic
The WBNOINVD instruction writes back all modified
cache lines in the processor’s internal cache to main memory
but does not invalidate (flush) the internal caches.

Reviewers: craig.topper, zvi, ashlykov

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D43817

llvm-svn: 329848
2018-04-11 20:09:09 +00:00
Artem Belevich dde3dc27ee [CUDA] Added --[no-]cuda-include-ptx=sm_XX|all option.
Currently we always include PTX into the fatbin along
with the GPU code.It about doubles the size of the GPU binary
we need to carry in the executable. These options allow control
inclusion of PTX into GPU binary.

This patch does not change the defaults, though we may consider
making no-PTX the default in the future.

Differential Revision: https://reviews.llvm.org/D45495

llvm-svn: 329737
2018-04-10 18:38:22 +00:00
Krzysztof Parzyszek 3163610010 [Hexagon] Remove -mhvx-double and the corresponding subtarget feature
Specifying the HVX vector length should be done via the -mhvx-length
option.

llvm-svn: 329077
2018-04-03 15:59:10 +00:00
Heejin Ahn 8b6af22e60 [WebAssembly] Add exception handling option
Summary: Add exception handling option to clang.

Reviewers: dschuff

Subscribers: jfb, sbc100, jgravelle-google, sunfish, cfe-commits

Differential Revision: https://reviews.llvm.org/D43681

llvm-svn: 326517
2018-03-02 00:39:16 +00:00
Scott Linder a2fbcef8ee [DebugInfo] Support DWARF v5 source code embedding extension
In DWARF v5 the Line Number Program Header is extensible, allowing values with
new content types. This vendor extension to DWARF v5 allows source text to be
embedded directly in the line tables of the debug line section.

Add new flag (-g[no-]embed-source) to Driver and CC1 which indicates
that source should be passed through to LLVM during CodeGen.

Differential Revision: https://reviews.llvm.org/D42766

llvm-svn: 326102
2018-02-26 17:32:31 +00:00
Hans Wennborg d43f40df1c Support for the mno-stack-arg-probe flag
Adds support for this flag. There is also another piece for llvm
(separate review). More info:
https://bugs.llvm.org/show_bug.cgi?id=36221

By Ruslan Nikolaev!

Differential Revision: https://reviews.llvm.org/D43108

llvm-svn: 325901
2018-02-23 13:47:36 +00:00
Jonas Hahnfeld a180fc4503 [docs] Regenerate command line reference
llvm-svn: 325807
2018-02-22 17:10:28 +00:00
Craig Topper 596527bca6 [Docs] Re-generate command line documentation.
llvm-svn: 323235
2018-01-23 18:40:15 +00:00
Dan Gohman d0c4e1e9fc [WebAssembly] Add target flags for sign-ext opcodes.
Add -msign-ext and -mno-sign-ext to control the new sign-ext target
feature.

llvm-svn: 322967
2018-01-19 17:16:32 +00:00
Craig Topper 287c801540 [Docs] Re-generate command line documentation, primarily to get the icelake feature command line options in, but there were a couple other changes too.
llvm-svn: 321749
2018-01-03 18:29:12 +00:00
Craig Topper 9a724aa38f [Driver][CodeGen] Add -mprefer-vector-width driver option and attribute during CodeGen.
This adds a new command line option -mprefer-vector-width to specify a preferred vector width for the vectorizers. Valid values are 'none' and unsigned integers. The driver will check that it meets those constraints. Specific supported integers will be managed by the targets in the backend.

Clang will take the value and add it as a new function attribute during CodeGen.

This represents the alternate direction proposed by Sanjay in this RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-November/118734.html

The syntax here matches gcc, though gcc treats it as an x86 specific command line argument. gcc only allows values of 128, 256, and 512. I'm not having clang check any values.

Differential Revision: https://reviews.llvm.org/D40230

llvm-svn: 320419
2017-12-11 21:09:19 +00:00
Craig Topper 188252dd1e [Docs] Regenerate command line documentation.
llvm-svn: 320418
2017-12-11 21:09:16 +00:00
Martell Malone c950c651a4 Toolchain: Normalize dwarf, sjlj and seh eh
This is a re-apply of r319294.

adds -fseh-exceptions and -fdwarf-exceptions flags

clang will check if the user has specified an exception model flag,
in the absense of specifying the exception model clang will then check
the driver default and append the model flag for that target to cc1

-fno-exceptions has a higher priority then specifying the model

move __SEH__ macro definitions out of Targets into InitPreprocessor
behind the -fseh-exceptions flag

move __ARM_DWARF_EH__ macrodefinitions out of verious targets and into
InitPreprocessor behind the -fdwarf-exceptions flag and arm|thumb check

remove unused USESEHExceptions from the MinGW Driver

fold USESjLjExceptions into a new GetExceptionModel function that
gives the toolchain classes more flexibility with eh models

Reviewers: rnk, mstorsjo

Differential Revision: https://reviews.llvm.org/D39673

llvm-svn: 319297
2017-11-29 07:25:12 +00:00
Martell Malone 2fa25706ed Revert "Toolchain: Normalize dwarf, sjlj and seh eh"
This reverts rL319294.
The windows sanitizer does not like seh on x86.
Will re apply with None type for x86

llvm-svn: 319295
2017-11-29 06:51:27 +00:00
Martell Malone 390cfcb0b1 Toolchain: Normalize dwarf, sjlj and seh eh
adds -fseh-exceptions and -fdwarf-exceptions flags

clang will check if the user has specified an exception model flag,
in the absense of specifying the exception model clang will then check
the driver default and append the model flag for that target to cc1

clang cc1 assumes dwarf is the default if none is passed
and -fno-exceptions has a higher priority then specifying the model

move __SEH__ macro definitions out of Targets into InitPreprocessor
behind the -fseh-exceptions flag

move __ARM_DWARF_EH__ macrodefinitions out of verious targets and into
InitPreprocessor behind the -fdwarf-exceptions flag and arm|thumb check

remove unused USESEHExceptions from the MinGW Driver

fold USESjLjExceptions into a new GetExceptionModel function that
gives the toolchain classes more flexibility with eh models

Reviewers: rnk, mstorsjo

Differential Revision: https://reviews.llvm.org/D39673

llvm-svn: 319294
2017-11-29 06:25:13 +00:00
Craig Topper 164186617e [Docs] Regenerate the command line option reference.
llvm-svn: 318672
2017-11-20 18:07:43 +00:00
Vlad Tsyrklevich 634c601fe3 [CFI] Add CFI-icall pointer type generalization
Summary:
This change allows generalizing pointers in type signatures used for
cfi-icall by enabling the -fsanitize-cfi-icall-generalize-pointers flag.
This works by 1) emitting an additional generalized type signature
metadata node for functions and 2) llvm.type.test()ing for the
generalized type for translation units with the flag specified.

This flag is incompatible with -fsanitize-cfi-cross-dso because it would
require emitting twice as many type hashes which would increase artifact
size.

Reviewers: pcc, eugenis

Reviewed By: pcc

Subscribers: kcc

Differential Revision: https://reviews.llvm.org/D39358

llvm-svn: 317044
2017-10-31 22:39:44 +00:00