Commit Graph

94 Commits

Author SHA1 Message Date
Scott Constable 080dd10f7d Move RDF from Hexagon to Codegen
RDF is designed to be target agnostic. Therefore it would be useful to have it available for other targets, such as X86.

Based on a previous patch by Krzysztof Parzyszek

Differential Revision: https://reviews.llvm.org/D75932
2020-03-17 12:43:14 -07:00
Krzysztof Parzyszek 6bfc6577f2 [Hexagon] Remove support for V4
llvm-svn: 344791
2018-10-19 17:31:11 +00:00
Krzysztof Parzyszek 39a979c838 [Hexagon] Expand vgather pseudos during packetization
This will allow packetizing the vgather expansion with other instructions.

llvm-svn: 340028
2018-08-17 14:24:24 +00:00
Nico Weber 5d53aed419 Consistently sort add_subdirectory calls in lib/Target/*/CMakeLists.txt
llvm-svn: 330584
2018-04-23 12:49:34 +00:00
Nico Weber 1cbd096914 Sort targetgen calls in lib/Target/*/CMakeLists.
Makes it easier to see mistakes such as the one fixed in r329178 and makes
the different target CMakeLists more consistent.

Also remove some stale-looking comments from the Nios2 target cmakefile.

No intended behavior change.

llvm-svn: 329181
2018-04-04 12:37:44 +00:00
Krzysztof Parzyszek 7cfe7cbccc [Hexagon] Express calling conventions via .td file instead of hand-coding
Additionally, simplify the rest of the argument/parameter lowering code.

llvm-svn: 324737
2018-02-09 15:30:02 +00:00
Krzysztof Parzyszek 95614acc24 [Hexagon] Replace multiple vector extracts with store-load combinations
llvm-svn: 323561
2018-01-26 21:17:14 +00:00
Krzysztof Parzyszek a8ab1b75cb [Hexagon] Add support for Hexagon V65
llvm-svn: 320404
2017-12-11 18:57:54 +00:00
Krzysztof Parzyszek 7d37dd8902 [Hexagon] Generate HVX code for vector construction and access
Support for:
  - build vector,
  - extract vector element, subvector,
  - insert vector element, subvector,
  - shuffle.

llvm-svn: 319901
2017-12-06 16:40:37 +00:00
Krzysztof Parzyszek 64e5d7d3ae [Hexagon] Reorganize and update instruction patterns
llvm-svn: 316228
2017-10-20 19:33:12 +00:00
Krzysztof Parzyszek 7c9c05888c [Hexagon] Minimize number of repeated constant extenders
Each constant extender requires an extra instruction, which adds to the
code size and also reduces the number of available slots in an instruction
packet. In most cases, the value of a repeated constant extender could be
loaded into a register, and the instructions using the extender could be
replaced with their counterparts that use that register instead.

This patch adds a pass that tries to reduce the number of constant
extenders, including extenders which differ only in an immediate offset
known at compile time, e.g. @global and @global+12.

llvm-svn: 315735
2017-10-13 19:02:59 +00:00
Pranav Bhandarkar 931d0b7aff Enable the reuse of values computed in a previous loop iteration.
This patch adds a pass that removes the computation of provably redundant
expressions that have been computed earlier in a previous iteration. It
relies on the use of PHIs to identify loop carried dependences.

This is scalar replacement for vector types.

llvm-svn: 313925
2017-09-21 21:48:23 +00:00
Krzysztof Parzyszek fe58ca3218 [Hexagon] Remove unused .td files
llvm-svn: 294775
2017-02-10 19:54:00 +00:00
Krzysztof Parzyszek a72fad980c [Hexagon] Replace instruction definitions with auto-generated ones
llvm-svn: 294753
2017-02-10 15:33:13 +00:00
Krzysztof Parzyszek 49ffff12e5 [RDF] Extract the physical register information into a separate class
llvm-svn: 293510
2017-01-30 17:46:56 +00:00
Krzysztof Parzyszek c8b943860f [Hexagon] Add Hexagon-specific loop idiom recognition pass
llvm-svn: 293213
2017-01-26 21:41:10 +00:00
Krzysztof Parzyszek 39d14f3bc3 Reapply r286080 with a phony change in Hexagon's CMakeLists.txt
Cmake has not recognized that Hexagon.td has a new dependency in
HexagonPatterns.td. All changes to that file were not visible to
the build bots.

llvm-svn: 286084
2016-11-06 20:55:57 +00:00
Krzysztof Parzyszek a77fe4eef3 [RDF] Replace RegisterAliasInfo with target-independent code using lane masks
llvm-svn: 283122
2016-10-03 17:14:48 +00:00
Krzysztof Parzyszek 12e03aa5fe [Hexagon] Delete HexagonSelectCCInfo.td
This file is not used. The location assignment of call arguments and
return values is implemented directly in HexagonISelLowering.

llvm-svn: 278237
2016-08-10 16:23:53 +00:00
Ron Lieberman 8123b966cb [Hexagon] Generate vector printing instructions
llvm-svn: 277370
2016-08-01 19:36:39 +00:00
Krzysztof Parzyszek e95e95521c [Hexagon] Implement DFA based hazard recognizer
The post register allocator scheduler can generate poor schedules
because the scoreboard hazard recognizer is unable to identify
hazards for Hexagon precisely. Instead, Hexagon should use a DFA
based hazard recognizer.

Patch by Brendon Cahoon.

llvm-svn: 277143
2016-07-29 13:59:09 +00:00
Krzysztof Parzyszek 167d918225 [Hexagon] Implement MI-level constant propagation
llvm-svn: 277028
2016-07-28 20:01:59 +00:00
NAKAMURA Takumi 2eec13680e Touch Hexagon/CMakeLists.txt to regenerate build files, since r268641 complains of missing HexagonAlias.td on ninja.
FIXME: TableGen.cmake globs *.td(s) with wildcards for deps. It is not good.
llvm-svn: 268666
2016-05-05 19:28:01 +00:00
Krzysztof Parzyszek f5cbac93eb [Hexagon] Optimize addressing modes for load/store
Patch by Jyotsna Verma.

llvm-svn: 268051
2016-04-29 15:49:13 +00:00
Krzysztof Parzyszek 7b59ae28aa [Hexagon] Implement branch relaxation
Patch by Sirish Pande.

llvm-svn: 266792
2016-04-19 18:30:18 +00:00
Krzysztof Parzyszek 7793ddb043 [Hexagon] Optimize stack slot spills
Replace spills to memory with spills to registers, if possible. This
applies mostly to predicate registers (both scalar and vector), since
they are very limited in number. A spill of a predicate register may
happen even if there is a general-purpose register available. In cases
like this the stack spill/reload may be eliminated completely.

This optimization will consider all stack objects, regardless of where
they came from and try to match the live range of the stack slot with
a dead range of a register from an appropriate register class.

llvm-svn: 260758
2016-02-12 22:53:35 +00:00
Krzysztof Parzyszek 7ce3dbcb57 [Hexagon] Remove HexagonExpandPredSpillCode pass
This code is dead. The expansion is now done in HexagonFrameLowering.

llvm-svn: 260691
2016-02-12 17:09:58 +00:00
Krzysztof Parzyszek 1279881315 [Hexagon] Implement RDF-based post-RA optimizations
- Handle simple cases of register copies (what current RDF CP allows).
- Hexagon-specific dead code elimination: handles dead address updates
  in post-increment instructions.

llvm-svn: 257504
2016-01-12 19:09:01 +00:00
Krzysztof Parzyszek c09d630e50 RDF: Copy propagation
This is a very limited implementation of DFG-based copy propagation.
It only handles actual COPY instructions (does not handle other equivalents
such as add-immediate with a 0 operand).
The major limitation is that it does not update the DFG: that will be the
change required to make it more robust (hopefully coming up soon).

llvm-svn: 257490
2016-01-12 17:23:48 +00:00
Krzysztof Parzyszek 6f4000e763 RDF: Dead code elimination
Utility class to perform DFG-based dead code elimination.

llvm-svn: 257485
2016-01-12 17:01:16 +00:00
Krzysztof Parzyszek acdff46a9c RDF: Implement register liveness analysis
Compute block live-ins and operand kill flags from the DFG.

llvm-svn: 257480
2016-01-12 15:56:33 +00:00
Krzysztof Parzyszek b5b5a1d7ad Register Data Flow: data flow graph
Target independent, SSA-based data flow framework for representing
data flow between physical registers.

This commit implements the creation of the actual data flow graph.

llvm-svn: 257477
2016-01-12 15:09:49 +00:00
Colin LeMahieu 7cd0892729 [Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission.
llvm-svn: 252443
2015-11-09 04:07:48 +00:00
Krzysztof Parzyszek ced9941cd4 [Hexagon] Bit-based instruction simplification
Analyze bit patterns of operands and values of instructions to perform
various simplifications, dead/redundant code elimination, etc.

llvm-svn: 250868
2015-10-20 22:57:13 +00:00
Krzysztof Parzyszek 055c5fd74e [Hexagon] Remove unnecessary argument sign extends
llvm-svn: 250724
2015-10-19 19:10:48 +00:00
Krzysztof Parzyszek a7c5f0409c [Hexagon] Split double registers
llvm-svn: 250549
2015-10-16 20:38:54 +00:00
Krzysztof Parzyszek aec39c68ae [Hexagon] Delete lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp
llvm-svn: 250543
2015-10-16 19:51:53 +00:00
Krzysztof Parzyszek 5b7dd0cdf9 [Hexagon] Merge adjacent stores
llvm-svn: 250542
2015-10-16 19:43:56 +00:00
Krzysztof Parzyszek fb33824efd [Hexagon] Add an early if-conversion pass
llvm-svn: 249423
2015-10-06 15:49:14 +00:00
Krzysztof Parzyszek 73e66f323a [Hexagon] Implement TargetTransformInfo for Hexagon
Author: Brendon Cahoon <bcahoon@codeaurora.org>
llvm-svn: 244089
2015-08-05 18:35:37 +00:00
Krzysztof Parzyszek 921722049d [Hexagon] Generate MUX from conditional transfers when dot-new not possible
llvm-svn: 242711
2015-07-20 21:23:25 +00:00
Krzysztof Parzyszek 758744706a [Hexagon] Generate instructions for operations on predicate registers
Convert logical operations on general-purpose registers to the correspon-
ding operations on predicate registers.

llvm-svn: 242186
2015-07-14 19:30:21 +00:00
Krzysztof Parzyszek a0ecf07c0b [Hexagon] Generate "extract" instructions more aggressively
Generate extract instructions (via intrinsics) before the DAG combiner
folds shifts into unrecognizable forms.

llvm-svn: 242163
2015-07-14 17:07:24 +00:00
Krzysztof Parzyszek 79b2433e7c [Hexagon] Implement commoning of GetElementPtr instructions
llvm-svn: 241714
2015-07-08 19:22:28 +00:00
Krzysztof Parzyszek 21b53a5120 [Hexagon] Generate "insert" instructions more aggressively
llvm-svn: 241683
2015-07-08 14:47:34 +00:00
Krzysztof Parzyszek d19b4767ff Revert 241681: causes Windows builds to fail
llvm-svn: 241682
2015-07-08 14:34:13 +00:00
Krzysztof Parzyszek 712b15b45e [Hexagon] Generate "insert" instructions more aggressively
llvm-svn: 241681
2015-07-08 14:22:27 +00:00
Krzysztof Parzyszek e53b31a593 [Hexagon] Implement bit-tracking facility with specifics for Hexagon
This includes code that is intended to be target-independent as well
as the Hexagon-specific details. This is just the framework without
any users.

llvm-svn: 241595
2015-07-07 15:16:42 +00:00
Krzysztof Parzyszek c05dff1792 Expand MUX instructions early on Hexagon
This time with all files included.

llvm-svn: 233696
2015-03-31 13:35:12 +00:00
Krzysztof Parzyszek 8c4fd2bdeb Revert 233694. Weak SVN-fu.
llvm-svn: 233695
2015-03-31 13:32:32 +00:00