Commit Graph

378638 Commits

Author SHA1 Message Date
Jessica Paquette dcb5b5f1f2 Revert "[GlobalISel] Walk through hints in getDefIgnoringCopies et al"
This reverts commit 4580acf675.

Reverting while looking into some test failures.
2021-01-28 14:37:57 -08:00
Jessica Paquette 4580acf675 [GlobalISel] Walk through hints in getDefIgnoringCopies et al
Treat hint instructions like G_ASSERT_ZEXT like COPY instructions in helpers
which walk through copies.

This ensures that instructions like G_ASSERT_ZEXT won't impact any optimizations
that rely on these helpers.

Differential Revision: https://reviews.llvm.org/D95577
2021-01-28 14:27:00 -08:00
Tony Tye 231f418295 [NFC][AMDGPU] Correct name of DWARF CFA extensions
Add LLVM to the DW_CFA_LLVM_def_aspace_cfa and
DW_CFA_LLVM_def_aspace_cfa_sf DWARF extensions.

Reviewed By: scott.linder

Differential Revision: https://reviews.llvm.org/D95640
2021-01-28 22:25:33 +00:00
MaheshRavishankar 98835e3d98 [mlir][Linalg] Enable TileAndFusePattern to work with tensors.
Differential Revision: https://reviews.llvm.org/D94531
2021-01-28 14:13:01 -08:00
Roman Lebedev 056385921d
[ScalarizeMaskedMemIntrin] Preserve Dominator Tree, if avaliable
This de-pessimizes the arguably more usual case of no masked mem intrinsics,
and gets rid of one more Dominator Tree recalculation.

As per llvm/test/CodeGen/X86/opt-pipeline.ll,
there's one more Dominator Tree recalculation left, we could get rid of.
2021-01-29 01:11:36 +03:00
Roman Lebedev 577fdcaa93
[PartiallyInlineLibCalls] Preserve Dominator Tree, if avaliable
This doesn't get rid of any Dominator Tree recalculations just yet,
there is one more pass to update..
2021-01-29 01:11:36 +03:00
Roman Lebedev 573f74117b
[NFC][ScalarizeMaskedMemIntrin] scalarizeMaskedCompressStore(): port to SplitBlockAndInsertIfThen()
Makes Dominator Tree preservation in a followup patch somewhat easier.
2021-01-29 01:11:35 +03:00
Roman Lebedev 2e4bb3f119
[NFC][ScalarizeMaskedMemIntrin] scalarizeMaskedExpandLoad(): port to SplitBlockAndInsertIfThen()
Makes Dominator Tree preservation in a followup patch somewhat easier.
2021-01-29 01:11:35 +03:00
Roman Lebedev e8efc03a1e
[NFC][ScalarizeMaskedMemIntrin] scalarizeMaskedScatter(): port to SplitBlockAndInsertIfThen()
Makes Dominator Tree preservation in a followup patch somewhat easier.
2021-01-29 01:11:35 +03:00
Roman Lebedev 1356399a11
[NFC][ScalarizeMaskedMemIntrin] scalarizeMaskedGather(): port to SplitBlockAndInsertIfThen()
Makes Dominator Tree preservation in a followup patch somewhat easier.
2021-01-29 01:11:34 +03:00
Roman Lebedev 22b8421156
[NFC][ScalarizeMaskedMemIntrin] scalarizeMaskedStore(): port to SplitBlockAndInsertIfThen()
Makes Dominator Tree preservation in a followup patch somewhat easier.
2021-01-29 01:11:34 +03:00
Roman Lebedev 0ea45a412a
[NFC][ScalarizeMaskedMemIntrin] scalarizeMaskedLoad(): port to SplitBlockAndInsertIfThen()
Makes Dominator Tree preservation in a followup patch somewhat easier.
2021-01-29 01:11:34 +03:00
Roman Lebedev 394685481c
[NFC][PartiallyInlineLibCalls] Port to SplitBlockAndInsertIfThen()
This makes follow-up patch for Dominator Tree preservation
somewhat more straight-forward.
2021-01-29 01:11:33 +03:00
Roman Lebedev 2de2d84ed0
[NFC][EntryExitInstrumenter] Mark Dominator Tree as preserved in legacy-PM too
This is correctly handled in new-PM wrappers, but not in old-PM.
2021-01-29 01:11:33 +03:00
Cassie Jones f22f4557a7 [GlobalISel] Implement widenScalar for carry-in add/sub
These are widened to a wider UADDE/USUBE, with the overflow value
unused, and with the same synthesis of a new overflow value as for the
O operations.

Reviewed By: paquette

Differential Revision: https://reviews.llvm.org/D95326
2021-01-28 17:06:24 -05:00
Jessica Paquette 24261729a4 [GlobalISel] Add G_ASSERT_ZEXT
This adds a generic opcode which communicates that a type has already been
zero-extended from a narrower type.

This is intended to be similar to AssertZext in SelectionDAG.

For example,

```
%x_was_extended:_(s64) = G_ASSERT_ZEXT %x, 16
```

Signifies that the top 48 bits of %x are known to be 0.

This is useful in cases like this:

```
define i1 @zeroext_param(i8 zeroext %x) {
  %cmp = icmp ult i8 %x, -20
  ret i1 %cmp
}
```

In AArch64, `%x` must use a 32-bit register, which is then truncated to a 8-bit
value.

If we know that `%x` is already zero-ed out in the relevant high bits, we can
avoid the truncate.

Currently, in GISel, this looks like this:

```
_zeroext_param:
  and w8, w0, #0xff ; We don't actually need this!
  cmp w8, #236
  cset w0, lo
  ret
```

While SDAG does not produce the truncation, since it knows that it's
unnecessary:

```
_zeroext_param:
  cmp w0, #236
  cset w0, lo
  ret
```

This patch

- Adds G_ASSERT_ZEXT
- Adds MIRBuilder support for it
- Adds MachineVerifier support for it
- Documents it

It also puts G_ASSERT_ZEXT into its own class of "hint instruction." (There
should be a G_ASSERT_SEXT in the future, maybe a G_ASSERT_ALIGN as well.)

This allows us to skip over hints in the legalizer etc. These can then later
be selected like COPY instructions or removed.

Differential Revision: https://reviews.llvm.org/D95564
2021-01-28 13:58:37 -08:00
AndreyChurbanov ac70a53653 [OpenMP] NFC: disabled two flakey tests as the bug in libomp not fixed yet 2021-01-29 00:54:13 +03:00
Greg Clayton f8122d3532 Add the ability to extract the unwind rows from DWARF Call Frame Information.
This patch adds the ability to evaluate the state machine for CIE and FDE unwind objects and produce a UnwindTable with all UnwindRow objects needed to unwind registers. It will also dump the UnwindTable for each CIE and FDE when dumping DWARF .debug_frame or .eh_frame sections in llvm-dwarfdump or llvm-objdump. This allows users to see what the unwind rows actually look like for a given CIE or FDE instead of just seeing a list of opcodes.

This patch adds new classes: UnwindLocation, RegisterLocations, UnwindRow, and UnwindTable.

UnwindLocation is a class that describes how to unwind a register or Call Frame Address (CFA).

RegisterLocations is a class that tracks registers and their UnwindLocations. It gets populated when parsing the DWARF call frame instruction opcodes for a unwind row. The registers are mapped from their register numbers to the UnwindLocation in a map.

UnwindRow contains the result of evaluating a row of DWARF call frame instructions for the CIE, or a row from a FDE. The CIE can produce a set of initial instructions that each FDE that points to that CIE will use as the seed for the state machine when parsing FDE opcodes. A UnwindRow for a CIE will not have a valid address, whille a UnwindRow for a FDE will have a valid address.

The UnwindTable is a class that contains a sorted (by address) vector of UnwindRow objects and is the result of parsing all opcodes in a CIE, or FDE. Parsing a CIE should produce a UnwindTable with a single row. Parsing a FDE will produce a UnwindTable with one or more UnwindRow objects where all UnwindRow objects have valid addresses. The rows in the UnwindTable will be sorted from lowest Address to highest after parsing the state machine, or an error will be returned if the table isn't sorted. To parse a UnwindTable clients can use the following methods:

    static Expected<UnwindTable> UnwindTable::create(const CIE *Cie);
    static Expected<UnwindTable> UnwindTable::create(const FDE *Fde);

A valid table will be returned if the DWARF call frame instruction opcodes have no encoding errors. There are a few things that can go wrong during the evaluation of the state machine and these create functions will catch and return them.

Differential Revision: https://reviews.llvm.org/D89845
2021-01-28 13:39:17 -08:00
Reid Kleckner bacf9cf2c5 Revert "[PDB] Defer relocating .debug$S until commit time and parallelize it"
This reverts commit 1a9bd5b813.

I suspect that this patch may have caused https://crbug.com/1171438.
2021-01-28 13:17:27 -08:00
Petr Hosek 1daaa6432e [CMake][libc] Support cross-compiling libc-hdrgen
This is useful when cross-compiling libc to another target in which
case we first need to compile libc-hdrgen for host. We rely on the
existing LLVM CMake infrastructure for that.

Differential Revision: https://reviews.llvm.org/D95205
2021-01-28 13:13:06 -08:00
Petr Hosek c4819eec1a [CMake][libc] Don't do CPU feature detection when cross-compiling
We won't be able to run the compiled program since it will be compiled
for different system. We instead allow passing the CPU features via
CMake option in that case.

Differential Revision: https://reviews.llvm.org/D95203
2021-01-28 12:54:37 -08:00
Stephen Kelly 3c79734f29 [ASTMatchers] Add invocation matcher
Differential Revision: https://reviews.llvm.org/D94865
2021-01-28 20:47:09 +00:00
Stephen Kelly 6f0df3cddb [ASTMatchers] Avoid pathological traversal over nested lambdas
Differential Revision: https://reviews.llvm.org/D95573
2021-01-28 20:45:45 +00:00
Duncan P. N. Exon Smith 39ecfe6143 Support: Simplify __HAIKU__ #ifdef in llvm::sys::Wait, NFC
This just reduces the amount of code in the `#ifndef` block as a
follow-up to 5c1cea6f40.
2021-01-28 12:28:12 -08:00
Mike Edwards fe190cf6c9 Removing the main to master sync GitHub workflow. 2021-01-28 12:18:25 -08:00
Albion Fung 2e470e03b4 [PowerPC][Power10] Fix XXSPLI32DX not correctly exploiting specific cases
Some cases may be transformed into 32 bit splats before hitting the boolean statement, which may cause incorrect behaviour and provide XXSPLTI32DX with the incorrect values of splat. The condition was reversed so that the shortcut prevents this problem.

Differential Revision: https://reviews.llvm.org/D95634
2021-01-28 15:17:32 -05:00
David Blaikie 85b7b5625a Fix memory leak in 4318028cd2 2021-01-28 12:08:23 -08:00
Hanhan Wang 2c7cc5fd20 Revert "[mlir][Linalg] Replace SimplePad with PadTensor in hoist-padding"
This reverts commit 1e790b745d.

Differential Revision: https://reviews.llvm.org/D95636
2021-01-28 11:25:02 -08:00
Hanhan Wang 1e790b745d [mlir][Linalg] Replace SimplePad with PadTensor in hoist-padding
This is the last revision to migrate using SimplePadOp to PadTensorOp, and the
SimplePadOp is removed in the patch. Update a bit in SliceAnalysis because the
PadTensorOp takes a region different from SimplePadOp. This is not covered by
LinalgOp because it is not a structured op.

Also, remove a duplicated comment from cpp file, which is already described in a
header file. And update the pseudo-mlir in the comment.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D95615
2021-01-28 11:09:57 -08:00
Thomas Lively 4b68b64dcc [WebAssembly] Prototype i8x16 to i32x4 widening instructions
As proposed in https://github.com/WebAssembly/simd/pull/395 and matching the
opcodes used in V8:
https://chromium-review.googlesource.com/c/v8/v8/+/2617385/4/src/wasm/wasm-opcodes.h

Differential Revision: https://reviews.llvm.org/D95557
2021-01-28 10:59:32 -08:00
Jacques Pienaar acaf85f700 Add convenience function for checking arrays of shapes compatible.
Expand existing one to handle the common case for verifying compatible
is existing and inferred. This considers arrays equivalent if they they
have the same size and pairwise compatible elements.
2021-01-28 10:47:08 -08:00
Aart Bik 8af0ccf5a4 [sparse][mlir] give all sparse kernels an explicit "output" tensor
Rationale:
Providing an output tensor, even if one is not used as input to
the kernel provides the right pattern for using lingalg sparse
kernels (in contrast with reusing a tensor just to provide the shape).
This prepares proper bufferization that will follow.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D95587
2021-01-28 10:41:17 -08:00
Nico Weber eae50bb210 [gn build] (manually) port 081c1db02d more 2021-01-28 13:32:49 -05:00
Nico Weber 8c54583b2e [gn build] (manually) port 3b625060fc 2021-01-28 13:26:37 -05:00
David Blaikie 4318028cd2 DebugInfo: Add a DWARF FORM extension for addrx+offset references to reduce relocations
This is an alternative to the use of complex DWARF expressions for
addresses - shaving off a few extra bytes of expression overhead.
2021-01-28 10:20:02 -08:00
Alex Zinenko d6be277347 [mlir] turn complex-to-llvm into a partial conversion
It is no longer necessary to also convert other "standard" ops along with the
complex dialect: the element types are now built-in integers or floating point
types, and the top-level cast between complex and struct is automatically
inserted and removed in progressive lowering.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D95625
2021-01-28 19:14:01 +01:00
Wouter van Oortmerssen 275c6af7d7 [WebAssembly] Fix Fast ISEL not lowering 64-bit function pointers
Differential Revision: https://reviews.llvm.org/D95410
2021-01-28 10:05:29 -08:00
Nico Weber 658398c842 [gn build] (semi-manually) port 081c1db02d 2021-01-28 13:05:10 -05:00
Jay Foad 39ef0965df [AMDGPU] Simplify some RUN lines. NFC. 2021-01-28 17:57:55 +00:00
Christian Sigg 51457cd506 [mlir] NFC: split --shared-libs option into multiple lines. 2021-01-28 18:54:05 +01:00
Adrian Prantl 62140d943c Better document the limitations of coro::salvageDebugInfo()
and fix a few edge cases that show up in the Swift compiler but
weren't caught by the existing tests. Most notably the old code wasn't
salvaging load operations correctly. The patch also gets rid of the
LoadFromFramePtr argument and replaces it with a more generalized
mechanism.
2021-01-28 09:53:19 -08:00
Mircea Trofin cfcc1110d7 [NFC] Disallow unused prefixes under clang/test/CodeGenCXX
The only test that needed change had 'QUAL' as an unused prefix. The
rest of the changes are to simplify the prefix lists.

Differential Revision: https://reviews.llvm.org/D95499
2021-01-28 09:47:21 -08:00
Fangrui Song b3af96d07b [llvm-nm] Display defined weak STT_GNU_IFUNC symbols as 'i'
This patch makes the behavior match GNU nm.
Note: undefined STT_GNU_IFUNC symbols use 'U'.

Differential Revision: https://reviews.llvm.org/D95461
2021-01-28 09:46:05 -08:00
Casey Carter 2dd0c4d846 [libcxx][test] Update directory_entry test for C++20
P1614R2 removes most of `directory_entry`'s member comparison operators, leaving only `operator==` and `operator<=>`. This test should require the comparison expressions to be valid rather than require the member functions to be present so it is correct in both C++17 and C++20 modes.
2021-01-28 09:40:54 -08:00
Walter Erquinigo 0bca9a7ce2 Fix lldb-vscode builds on Windows targeting POSIX
@stella.stamenova found out that lldb-vscode's Win32 macros were failing
when building on windows targetings POSIX platforms.

I'm changing these macros for LLVM_ON_UNIX, which should be more
accurate.
2021-01-28 09:36:13 -08:00
Nicolas Vasilache 0f2901201e [mlir] Fix test by adapting to C util functions moving to libmlir_c_runner_utils 2021-01-28 17:35:51 +00:00
Craig Topper c5d4b77b17 [RISCV] Remove isel patterns for Zbs *W instructions.
These instructions have been removed from the 0.94 bitmanip spec.
We should focus on optimizing the codegen without using them.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D95302
2021-01-28 09:33:56 -08:00
Mark de Wever 18fe3fe0e7 [libc++] Implements concept constructible_from
Implements parts of:
- P0898R3 Standard Library Concepts
- P1754 Rename concepts to standard_case for C++20, while we still can

Depends on: D91004

Reviewed By: ldionne, cjdb, #libc

Differential Revision: https://reviews.llvm.org/D91986
2021-01-28 18:32:47 +01:00
Aart Bik 6640b9aa8a [mlir][sparse] use typenames for opaque pointers
Makes intent more readable

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D95592
2021-01-28 09:23:11 -08:00
Craig Topper ae82a8c863 [RISCV] Add support for scalable vector fneg using vfsgnjn.vv
Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D95568
2021-01-28 09:11:49 -08:00