3b775b8cc3
Rename immLUiOpnd.
...
llvm-svn: 147519
2012-01-04 03:09:26 +00:00
b89a4bfe41
- Define base classes for Jump-and-link instructions and make 32-bit and 64-bit
...
versions derive from them.
- JALR64 is not needed since N64 does not emit jal.
- Add template parameter to BranchLink that sets the rt field.
- Fix the set of temporary registers for O32 and N64.
llvm-svn: 147518
2012-01-04 03:02:47 +00:00
964c891e61
Fix bug in zero-store peephole pattern reported in pr11615.
...
The patch and test case were originally written by Mans Rullgard.
llvm-svn: 147024
2011-12-21 00:31:10 +00:00
43c1ff4db3
Add definition of WSBH (Word Swap Bytes within Halfwords), which is an
...
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
WSBW is removed since it is not an instruction the current architectures
support.
llvm-svn: 147015
2011-12-20 23:47:44 +00:00
0cee2045c9
Add patterns for matching extloads with 64-bit address. The patterns are enabled
...
only when the target ABI is N64.
llvm-svn: 147001
2011-12-20 22:33:53 +00:00
9b9bd1cc15
Add a pattern for matching zero-store with 64-bit address. The pattern is enabled
...
only when the target ABI is N64.
llvm-svn: 146992
2011-12-20 21:50:49 +00:00
db47e0c49d
Add patterns for matching immediates whose lower 16-bit is cleared. These
...
patterns emit a single LUi instruction instead of a pair of LUi and ORi.
llvm-svn: 146900
2011-12-19 20:21:18 +00:00
9e1d369e3c
Tidy up. Simplify logic. No functional change intended.
...
llvm-svn: 146896
2011-12-19 19:52:25 +00:00
5d5e0d819d
Emit B (unconditional branch) when -relocation-model=pic and J (jump) when
...
-relocation-model=static.
llvm-svn: 146432
2011-12-12 22:39:35 +00:00
5ee8464e48
Rename WrapperPIC. It is now used for both pic and static.
...
llvm-svn: 146232
2011-12-09 01:53:17 +00:00
dee6c8275c
Implement 64-bit support for thread local storage handling.
...
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
llvm-svn: 146175
2011-12-08 20:34:32 +00:00
4350c183d4
Modify class ReadHardware and add definition of 64-bit version of instruction
...
RDHWR.
llvm-svn: 146101
2011-12-07 23:31:26 +00:00
6820eebde1
Define base class for WrapperPICPat.
...
llvm-svn: 146081
2011-12-07 21:54:54 +00:00
4a04a56a36
Fix 64-bit immediate patterns.
...
llvm-svn: 146059
2011-12-07 20:10:24 +00:00
0c24d8a406
Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter
...
llvm-svn: 145912
2011-12-06 03:34:48 +00:00
9b8ac674bc
Split ExtIns into two base classes and have instructions EXT and INS derive from
...
them.
llvm-svn: 145852
2011-12-05 21:14:28 +00:00
049e9e4d22
This patch makes the following changes necessary for MIPS' direct code emission.
...
- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).
llvm-svn: 145113
2011-11-23 22:19:28 +00:00
7b8547c4d0
Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool
...
nodes.
llvm-svn: 144841
2011-11-16 22:39:56 +00:00
6d617ceca2
64-bit jump register instruction.
...
llvm-svn: 144840
2011-11-16 22:36:01 +00:00
c85e3ff334
Mips MC object code emission improvements:
...
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter
llvm-svn: 144414
2011-11-11 22:58:42 +00:00
21cbc25bbb
64-bit atomic instructions.
...
llvm-svn: 144372
2011-11-11 04:14:30 +00:00
4bdfec57ba
Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
...
llvm-svn: 144370
2011-11-11 04:06:38 +00:00
0009dc2088
64-bit versions of jal, jalr and bal.
...
llvm-svn: 144368
2011-11-11 04:03:54 +00:00
2b8d1f163f
Add definition of 64-bit load upper immediate.
...
llvm-svn: 143994
2011-11-07 19:10:49 +00:00
770f0646db
Make the type of shift amount i32 in order to reduce the number of shift
...
instruction definitions.
llvm-svn: 143989
2011-11-07 18:59:49 +00:00
2312a3aaa0
Final patch that completes old JIT support for Mips:
...
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.
Patch by Sasa Stankovic
llvm-svn: 142378
2011-10-18 17:50:36 +00:00
a7e0b90897
Add definitions of conditional moves with 64-bit operands. Comment out code for
...
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed.
llvm-svn: 142226
2011-10-17 18:53:29 +00:00
975bfc9b45
Move class and instruction definitions for conditional moves to a seperate file.
...
llvm-svn: 142220
2011-10-17 18:43:19 +00:00
33fe8f908c
Redefine count-leading 0s and 1s instructions.
...
llvm-svn: 142216
2011-10-17 18:26:37 +00:00
8c446be204
Redefine mfhi/lo and mthi/lo instructions.
...
llvm-svn: 142214
2011-10-17 18:24:15 +00:00
0317b65367
Redefine multiply and divide instructions.
...
llvm-svn: 142211
2011-10-17 18:21:24 +00:00
2736bbc09e
Add definition of a base class for logical shift/rotate instructions with two
...
source registers and redefine 32-bit and 64-bit instructions.
llvm-svn: 142210
2011-10-17 18:17:58 +00:00
73081309c3
Add definition of a base class for logical shift/rotate immediate instructions
...
and have 32-bit and 64-bit instructions derive from it.
llvm-svn: 142207
2011-10-17 18:06:56 +00:00
e3f27b79dc
Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.
...
llvm-svn: 142205
2011-10-17 18:01:00 +00:00
3261c0fa6e
Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.
...
llvm-svn: 141761
2011-10-12 01:05:13 +00:00
c57febff4a
Fix encoding of 32-bit integer instructions. Change names of operands and nodes.
...
Remove unused classes.
llvm-svn: 141757
2011-10-12 00:56:06 +00:00
0f4ecf7548
Change name of class to ArithOverflowR.
...
llvm-svn: 141743
2011-10-11 23:43:48 +00:00
8f0d549c4c
Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical
...
instructions with two register operands derive from it.
llvm-svn: 141742
2011-10-11 23:38:52 +00:00
8d4f74a6b1
Fix comment.
...
llvm-svn: 141737
2011-10-11 23:12:12 +00:00
ae5a9d6578
Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit
...
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.
llvm-svn: 141736
2011-10-11 23:05:46 +00:00
10ae11fd57
Remove unused PatLeaf.
...
llvm-svn: 141720
2011-10-11 21:53:08 +00:00
46a7994ac9
Remove redundancy in setcc patterns using multiclass.
...
llvm-svn: 141715
2011-10-11 21:40:01 +00:00
8c1c51045d
Use sltiu instead of sltu when a register operand and immediate are compared.
...
llvm-svn: 141708
2011-10-11 20:44:43 +00:00
7148bce86e
Add patterns for conditional branches with 64-bit register operands.
...
llvm-svn: 141696
2011-10-11 19:09:09 +00:00
f75add6236
Add support for 64-bit set-on-less-than instructions.
...
llvm-svn: 141695
2011-10-11 18:53:46 +00:00
4b6ac98fcf
Add support for conditional branch instructions with 64-bit register operands.
...
llvm-svn: 141694
2011-10-11 18:49:17 +00:00
b6d72cbeb9
Make changes necessary for supporting floating point load and store instructions
...
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
llvm-svn: 141623
2011-10-11 01:12:52 +00:00
be68f3c348
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
...
zextloadi32 for which there is no corresponding pseudo or real instruction.
llvm-svn: 141608
2011-10-11 00:27:28 +00:00
fd2d7dcc31
Change definitions of classes LoadM and StoreM in preparation for adding support
...
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.
llvm-svn: 141603
2011-10-11 00:11:12 +00:00
557c8e3443
Add patterns for unaligned load and store instructions and enable the
...
instruction selector to generate them.
llvm-svn: 141471
2011-10-08 02:24:10 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
...
llvm-svn: 141024
2011-10-03 21:06:13 +00:00
cdcc74563c
Add definitions of instructions which move values between 64-bit integer
...
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
llvm-svn: 141015
2011-10-03 19:28:44 +00:00
e96273e75d
Preparation for adding simple Mips64 instructions.
...
llvm-svn: 140443
2011-09-24 01:34:44 +00:00
f25c37e384
Make changes in instruction and pattern definitions so that tablegen does not
...
complain it cannot infer types in patterns. Fix a mistake in definition of
SDT_MipsExtractElementF64.
llvm-svn: 140354
2011-09-22 23:31:54 +00:00
bb49e721b8
Change the names of functions isMips* to hasMips*.
...
llvm-svn: 140214
2011-09-20 23:53:09 +00:00
fba4bd62b1
Add pattern used to match MipsLo, which is needed when the instruction selector
...
tries to match a dead MipsLo node (explanation in the link below).
http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead
llvm-svn: 139634
2011-09-13 20:13:58 +00:00
4444daeec5
Drop support for Mips1 and Mips2.
...
llvm-svn: 139405
2011-09-09 20:45:50 +00:00
2b8078a2cd
Clenup and fix encoding for Mips ins and ext instruction
...
llvm-svn: 137943
2011-08-18 16:30:49 +00:00
eea541ce4e
Changed definition of EXT and INS per Bruno's comments.
...
llvm-svn: 137892
2011-08-17 22:59:46 +00:00
b2e7558c40
Add support for half-word unaligned loads and stores.
...
llvm-svn: 137848
2011-08-17 18:49:18 +00:00
5360f88355
Add support for ext and ins.
...
llvm-svn: 137804
2011-08-17 02:05:42 +00:00
2fcc1cfdce
Define unaligned load and store.
...
llvm-svn: 137515
2011-08-12 21:30:06 +00:00
6d8c039ab1
Add isIndirectBranch flag.
...
llvm-svn: 137351
2011-08-11 21:05:37 +00:00
170581488f
Change name of class.
...
llvm-svn: 135550
2011-07-20 00:53:09 +00:00
969edcdf74
Define classes for definitions of atomic instructions.
...
llvm-svn: 135546
2011-07-20 00:23:01 +00:00
a4c09bce9b
Lower memory barriers to sync instructions.
...
llvm-svn: 135537
2011-07-19 23:30:50 +00:00
27292638bd
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from
...
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.
llvm-svn: 135415
2011-07-18 18:52:12 +00:00
28d6677a53
Remove unnecessary newline.
...
llvm-svn: 134645
2011-07-07 22:06:18 +00:00
9f6f6f6ecc
Rather than having printMemOperand change the way memory operands are printed
...
based on a modifier, split it into two functions.
llvm-svn: 134637
2011-07-07 20:54:20 +00:00
2e766ed2f8
Reverse order of operands of address operand mem so that the base operand comes
...
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.
llvm-svn: 134625
2011-07-07 18:57:00 +00:00
4c406e7457
Re-apply 132758 and 132768 which were speculatively reverted in 132777.
...
llvm-svn: 133494
2011-06-21 00:40:49 +00:00
f15601f19a
Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
...
llvm-svn: 132777
2011-06-09 16:03:19 +00:00
4e9af454f7
Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
...
dynamically allocated stack area was not set.
llvm-svn: 132758
2011-06-08 21:28:09 +00:00
d8373a4680
Add comments for wrapper node patterns in MipsInstrInfo.td.
...
llvm-svn: 132717
2011-06-07 18:00:14 +00:00
98fc4c8bbc
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
...
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.
Patch by Sasa Stankovic.
llvm-svn: 132323
2011-05-31 02:54:07 +00:00
bf3c1251e0
This patch implements the thread local storage. Implemented are General
...
Dynamic, Initial Exec and Local Exec TLS models.
Patch by Sasa Stankovic
llvm-svn: 132322
2011-05-31 02:53:58 +00:00
b406843fe5
Define a wrapper node for target constant nodes (tglobaladdr, etc.).
...
Need this to prevent emitting illegal conditional move instructions.
llvm-svn: 132240
2011-05-28 01:07:07 +00:00
46662e0f91
Coding style fixes. Added comments.
...
llvm-svn: 132063
2011-05-25 17:32:06 +00:00
2db176c4c1
Enable printing of immediates that do not fit in 16-bit. .cprestore can have
...
offsets that are larger than 0x10000.
llvm-svn: 132003
2011-05-24 21:22:21 +00:00
e50a3d16e9
Fix setting of isCommutable flag.
...
llvm-svn: 131233
2011-05-12 17:42:08 +00:00
5dc19f916c
Fix td file comments for Mips.
...
Patch by Liu <proljc@gmail.com>!
llvm-svn: 131086
2011-05-09 18:16:46 +00:00
0e7ee666b7
Lower BlockAddress node when relocation-model is static.
...
llvm-svn: 130131
2011-04-25 17:10:45 +00:00
e24891251c
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
...
llvm-svn: 129612
2011-04-15 21:51:11 +00:00
aef55c8801
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
...
llvm-svn: 129606
2011-04-15 21:00:26 +00:00
a535270d91
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
...
llvm-svn: 128650
2011-03-31 18:26:17 +00:00
434248a62c
Improve div/rem node handling on mips. Patch by Akira Hatanaka
...
llvm-svn: 127034
2011-03-04 21:03:24 +00:00
a744ef3f90
Expands register/immediate pairs when the immediate is too large to fit in 16-bit field. Patch by Akira Hatanaka
...
llvm-svn: 127032
2011-03-04 20:48:08 +00:00
f8198e4311
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
...
llvm-svn: 127027
2011-03-04 20:01:52 +00:00
db93ddb41b
Fixes addc pattern when immediate cannot be represented with 16-bit. Patch by Akira Hatanaka
...
llvm-svn: 127005
2011-03-04 17:59:18 +00:00
ed874eff93
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
...
llvm-svn: 127003
2011-03-04 17:51:39 +00:00
4dc73fa075
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka
...
llvm-svn: 123760
2011-01-18 19:29:17 +00:00
2a0a3b43d7
Flag -> Glue, the ongoing saga
...
llvm-svn: 122513
2010-12-23 18:28:41 +00:00
d47180e45e
Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka
...
llvm-svn: 121377
2010-12-09 17:32:30 +00:00
b9bfd0945a
Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again
...
llvm-svn: 121164
2010-12-07 19:04:14 +00:00
f0c6e3780d
Match a pattern generated by a dag combiner opt where:
...
(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))
Thanks to Akira for pointing that.
llvm-svn: 121163
2010-12-07 19:00:20 +00:00
03c0330176
Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>
...
llvm-svn: 118864
2010-11-12 00:38:32 +00:00
67fc18a493
Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks
...
llvm-svn: 118667
2010-11-10 02:13:22 +00:00
9c5c829d9a
Fix trailing whitespace and style, no functionality change
...
llvm-svn: 118515
2010-11-09 17:25:34 +00:00
92d57cee61
Don't call Predicate_* in Mips.
...
llvm-svn: 111468
2010-08-18 23:56:46 +00:00
72a364c107
fix emacs language spec's, patch by Edmund Grimley-Evans!
...
llvm-svn: 111241
2010-08-17 16:20:04 +00:00
Akira Hatanaka