4cd5187f5b
RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller.
...
llvm-svn: 131868
2011-05-22 21:41:23 +00:00
c7250faeb1
Add methods to parse the SEH directives to the COFFAsmParser. Implement some
...
of them, particularly the ones that don't take arguments. Also implement
.seh_proc and .seh_handler.
llvm-svn: 131866
2011-05-22 21:12:15 +00:00
bfe2c24c80
add a note.
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llvm-svn: 131863
2011-05-22 18:28:46 +00:00
162dfc3e6b
add some random notes.
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llvm-svn: 131862
2011-05-22 18:26:48 +00:00
2a746bfe36
Teach ValueTracking about x86 crc32 intrinsics.
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llvm-svn: 131861
2011-05-22 18:25:30 +00:00
7c99f19d9f
Carve out a place in instcombine to put transformations which work knowing that their
...
result is non-zero. Implement an example optimization (PR9814), which allows us to
transform:
A / ((1 << B) >>u 2)
into:
A >>u (B-2)
which we compile into:
_divu3: ## @divu3
leal -2(%rsi), %ecx
shrl %cl, %edi
movl %edi, %eax
ret
instead of:
_divu3: ## @divu3
movb %sil, %cl
movl $1, %esi
shll %cl, %esi
shrl $2, %esi
movl %edi, %eax
xorl %edx, %edx
divl %esi, %eax
ret
llvm-svn: 131860
2011-05-22 18:18:41 +00:00
a0c9c75df2
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
...
Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and
modified ARMDisassemblerCore.cpp a little bit.
llvm-svn: 131859
2011-05-22 17:51:04 +00:00
c4ca7ab7e7
Fix PR9815: I was trying to get out of "generating code and then
...
failing to form a memset, then having to delete it" but my approximation
isn't safe for self recurrent loops. Instead of doign a hack, just
do it the right way.
llvm-svn: 131858
2011-05-22 17:39:56 +00:00
ad964559ef
Add a parameter to ConstantFoldTerminator() that callers can use to ask it to also clean up the condition of any conditional terminator it folds to be unconditional, if that turns the condition into dead code. This just means it calls RecursivelyDeleteTriviallyDeadInstructions() in strategic spots. It defaults to the old behavior.
...
I also changed -simplifycfg, -jump-threading and -codegenprepare to use this to produce slightly better code without any extra cleanup passes (AFAICT this was the only place in -simplifycfg where now-dead conditions of replaced terminators weren't being cleaned up). The only other user of this function is -sccp, but I didn't read that thoroughly enough to figure out whether it might be holding pointers to instructions that could be deleted by this.
llvm-svn: 131855
2011-05-22 16:24:18 +00:00
1a1acc2191
fix PR9856, an incorrectly conservative assertion: a global can be
...
"stored once" even if its address is compared.
llvm-svn: 131849
2011-05-22 07:15:13 +00:00
f0d59072de
fix PR9841 by having GVN not process dead loads. This was
...
causing it to get into infinite loops when it would widen a
load (which can necessarily leave around dead loads).
llvm-svn: 131847
2011-05-22 07:03:34 +00:00
9f1d2ded13
fix a bug for hosts without round, PR8893.
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llvm-svn: 131842
2011-05-22 06:03:53 +00:00
bbc40ac474
move PR9408 here.
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llvm-svn: 131841
2011-05-22 05:45:06 +00:00
a68ec83b36
Teach the inliner to emit llvm.lifetime.start/end, to scope the local variables
...
of the inlinee to the code representing the original function.
llvm-svn: 131838
2011-05-22 05:22:10 +00:00
1d068cc0b0
switch to using a smallvector to avoid allocations for most normal size instructions.
...
llvm-svn: 131837
2011-05-22 04:53:24 +00:00
0388fb0ee2
tidy some things up.
...
llvm-svn: 131836
2011-05-22 04:52:24 +00:00
bc2daa0f93
Implement emission of all Win64 exception tables. Make the COFF streamer emit
...
these tables.
llvm-svn: 131833
2011-05-22 04:15:07 +00:00
1c8bd5ad7e
Make the COFF streamer emit unwind info when processing a .seh_handlerdata
...
directive.
Implement emission of Win64 EH unwind info.
Pull in <cassert> in MCWin64EH.h so it can use the assert() macro.
llvm-svn: 131832
2011-05-22 03:01:05 +00:00
e636022b4d
Don't allow unaligned offsets and sizes in the Win64 EH directives.
...
Also, fix threshold for 'Big' register saves.
llvm-svn: 131830
2011-05-22 00:56:20 +00:00
6078926e26
random comment cleanups.
...
llvm-svn: 131829
2011-05-22 00:50:53 +00:00
b5865ded27
remove StandardPasses, it has been replaced with PassManagerBuilder
...
llvm-svn: 131827
2011-05-22 00:30:45 +00:00
04120e9567
eliminate dependence on StandardPasses.h. The code generator's pass pipeline
...
should eventually convert to PMBuilder, but I don't plan to do this.
llvm-svn: 131819
2011-05-22 00:13:44 +00:00
babca9aee9
Add CreateLifetimeStart and CreateLifetimeEnd to the IRBuilder, with plans to
...
use these soon.
llvm-svn: 131812
2011-05-21 23:14:36 +00:00
5ec65765e6
Revert commit 131781, to see if it fixes the x86-64 dragonegg buildbot.
...
Original log message:
When BasicAA can determine that two pointers have the same base but
differ by a dynamic offset, return PartialAlias instead of MayAlias.
See the comment in the code for details. This fixes PR9971.
llvm-svn: 131809
2011-05-21 20:54:46 +00:00
4c0d9e2249
add a copy ctor to TargetLibraryInfo.
...
llvm-svn: 131806
2011-05-21 20:09:13 +00:00
3de2ddc578
PR7952: Make isa<> use the same logic as cast<>, so that they both work
...
consistently.
llvm-svn: 131803
2011-05-21 19:13:10 +00:00
e30b70073a
X86: smulo -> add is now done target-independently in DAGCombiner, remove the patterns.
...
llvm-svn: 131801
2011-05-21 18:32:01 +00:00
2fd48f2730
Implement mulo x, 2 -> addo x, x in DAGCombiner.
...
llvm-svn: 131800
2011-05-21 18:31:55 +00:00
fda5dc4968
Revert "InstCombine: Turn mul.with.overflow(X, 2) into the cheaper add.with.overflow(X, X)"
...
It's better to do this in codegen, mul.with.overflow(X, 2) is more canonical because it has only one use on "X".
llvm-svn: 131798
2011-05-21 18:31:42 +00:00
6879634efd
Don't allow .seh_handler and .seh_handlerdata directives inside chained
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unwind areas.
llvm-svn: 131795
2011-05-21 17:36:25 +00:00
8e8f59bdfb
A handler for a function in the Win64 EH scheme can be both an unwind handler
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and an exception handler. Handle that case.
Also, add an 'Emitted' member to the MCWin64EHUnwindInfo struct. It will be
needed later.
llvm-svn: 131791
2011-05-21 15:57:49 +00:00
691731eb9c
InstCombine: Turn mul.with.overflow(X, 2) into the cheaper add.with.overflow(X, X)
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llvm-svn: 131789
2011-05-21 09:22:06 +00:00
faeb520c97
Fix PR9978 by adding RIP to GR64_TC so it can be used as an address in PIC code. It
...
is already in GR64 for the same reasons. Since it isn't allocatable it can't cause
any problems.
llvm-svn: 131787
2011-05-21 04:13:49 +00:00
2df6c010aa
Use the correct register to access stack frame objects.
...
llvm-svn: 131785
2011-05-21 03:01:03 +00:00
f084fcd7fe
Insert instructions that copy $sp to or from $fp at the right locations.
...
llvm-svn: 131784
2011-05-21 02:29:26 +00:00
8b20187c82
When BasicAA can determine that two pointers have the same base but
...
differ by a dynamic offset, return PartialAlias instead of MayAlias.
See the comment in the code for details. This fixes PR9971.
llvm-svn: 131781
2011-05-21 01:05:08 +00:00
d5d0764b3b
Have Program::Wait return -2 for crashed and timeouts instead of embedding
...
info in the error message. Per Dan's request.
llvm-svn: 131780
2011-05-21 00:56:46 +00:00
54254008ba
Set the "LastFrameInst" field when streaming a .seh_setframe directive. This
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is needed for an upcoming patch.
llvm-svn: 131772
2011-05-21 00:09:04 +00:00
d7ee0fcac9
Fix PR9962 by properly constraining register classes in RemoveCopyByCommutingDef(). This
...
actually fixes most of the VerifyCoalescing failures in test-suite.
llvm-svn: 131768
2011-05-20 23:25:36 +00:00
0837692ac6
Change the order fixed objects are created in MipsTargetLowering::LowerCall in
...
preparation for reversing StackDirection.
Fixed objects are created in the following order:
1. Incoming arguments passed on stack.
2. va_arg objects (include both arguments that are passed in registers and
pointer to the location of the first va_arg argument).
3. $gp restore slot.
4. Outgoing arguments passed on stack.
5. Pointer to alloca'd space.
llvm-svn: 131767
2011-05-20 23:22:14 +00:00
1a1d4777b9
Fix typo. When will I learn?
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llvm-svn: 131765
2011-05-20 22:23:34 +00:00
60afcc2a6f
Add fast-isel support for byval calls on x86.
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llvm-svn: 131764
2011-05-20 22:21:04 +00:00
bc1feb1f25
Add .pdata and .xdata sections to the COFF TLOF implementation.
...
llvm-svn: 131763
2011-05-20 22:13:55 +00:00
8aded86edb
No reason not to allow defining the CFA as a reg w/ offset zero.
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llvm-svn: 131760
2011-05-20 21:50:09 +00:00
7c619f174a
In CC_MipsO32, allocate a stack space regardless of whether the argument is
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passed in register or on the stack.
llvm-svn: 131758
2011-05-20 21:39:54 +00:00
17c1d13ee4
Fix typo.
...
llvm-svn: 131757
2011-05-20 21:35:39 +00:00
83c4bb157a
Add support for frame info use of the .cfi_def_cfa directive.
...
llvm-svn: 131756
2011-05-20 21:23:17 +00:00
860b03b5f9
Add missing leading \t when printing .cfi_def_cfa in the asmstreamer.
...
llvm-svn: 131755
2011-05-20 21:22:37 +00:00
cae19e8671
Define functions that get/set maximum call frame size.
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llvm-svn: 131752
2011-05-20 20:11:17 +00:00
652bfdb1ab
adds some attributes to attribute section when cpu is "xscale"
...
(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
llvm-svn: 131751
2011-05-20 20:10:34 +00:00
1866808384
fixes target address tBL and tBLX and sets relocation type
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of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)
Patch by koan-sin tan.
llvm-svn: 131748
2011-05-20 20:01:01 +00:00
91f1d24736
Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.
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rdar://problem/8614450
llvm-svn: 131746
2011-05-20 19:04:40 +00:00
43407fe633
Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle
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saving and restoring them.
llvm-svn: 131745
2011-05-20 18:39:33 +00:00
f44aadf0fd
indvars: Prototyping Sign/ZeroExtend elimination without canonical IVs.
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No functionality enabled by default. Use -disable-iv-rewrite.
Extended IVUsers to keep track of the phi that represents the users' IV.
Added the WidenIV transform to replace a narrow IV with a wide IV
by doing a one-for-one replacement of IV users instead of expanding the
SCEV expressions. [sz]exts are removed and truncs are inserted.
llvm-svn: 131744
2011-05-20 18:25:42 +00:00
9a115a4bd2
Now that they're implemented, make the Win64 EH MCAsmStreamer methods call
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super.
llvm-svn: 131743
2011-05-20 18:19:22 +00:00
4fcd8250ae
Revert accidental commit.
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llvm-svn: 131739
2011-05-20 17:38:48 +00:00
24b31b6b7d
"Implement" the HandlerData Win64 EH method in the base MCStreamer.
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There's really nothing to implement. All this really does is swap to a
pseudo-section that later gets written to the unwind info struct. That
needs to be implemented in the object streamers.
llvm-svn: 131734
2011-05-20 16:06:22 +00:00
0bf26746d9
Rename the "sandybridge" subtarget to "corei7-avx", for GCC compatibility.
...
llvm-svn: 131730
2011-05-20 15:11:26 +00:00
cc7a928885
Remove noisy semicolons.
...
llvm-svn: 131724
2011-05-20 09:20:25 +00:00
e0a52df6e5
Fix PR9960 by teaching SimpleRegisterCoalescing::AdjustCopiesBackFrom() to preserve
...
the phikill flag.
llvm-svn: 131717
2011-05-20 03:54:04 +00:00
b75279cbbd
indvars: minor cleanup in preparation for sign/zero extend elimination.
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llvm-svn: 131716
2011-05-20 03:37:48 +00:00
fe4f9d5977
Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic
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llvm-svn: 131714
2011-05-20 02:30:51 +00:00
7489faa0c1
Remove code that creates unnecessary frame objects.
...
llvm-svn: 131711
2011-05-20 01:45:06 +00:00
d738c0f7c9
Define variables and functions in MipsFunctionInfo.
...
This is the first of a series of patches that attempt to simplify handling of
stack frame objects.
llvm-svn: 131710
2011-05-20 01:17:58 +00:00
552f8c4819
Don't attempt to tail call optimize for Win64.
...
llvm-svn: 131709
2011-05-20 00:59:28 +00:00
e8d2e9eb35
Revert r131664 and fix it in instcombine instead. rdar://9467055
...
llvm-svn: 131708
2011-05-20 00:54:37 +00:00
2af60abad8
Fix PR9955 by only attaching load memory operands to load instructions and
...
similarly for stores. Now "make check" passes with the MachineVerifier forced
on with the VerifyCoalescing option!
llvm-svn: 131705
2011-05-19 23:44:34 +00:00
22da799428
Add fast-isel support for zeroext and signext ret instructions on x86.
...
llvm-svn: 131689
2011-05-19 22:16:13 +00:00
1edfb17bc2
Looks like OS X assemblers (including MC) don't like
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foo:
bar = foo
.quad bar
Avoid producing it. Fixes PR9951.
llvm-svn: 131687
2011-05-19 22:05:56 +00:00
8e129296fe
Misc code refactorings:
...
* Remove unnecessary arguments now that ForceExpAbs is a method.
* Use ForceExpAbs in EmitAbsValue.
llvm-svn: 131683
2011-05-19 21:40:34 +00:00
4014e5e208
Oddly people want to use the 'r' constraint for fp constants on x86.
...
Fixes rdar://9218925
Fixes PR9601
llvm-svn: 131682
2011-05-19 21:33:47 +00:00
de745ba396
Implement the EndProlog Win64 EH method on the base MCStreamer.
...
llvm-svn: 131679
2011-05-19 21:24:54 +00:00
d0c937d4b2
This fixes one divergence between LLVM and binutils for ARM in the
...
text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
llvm-svn: 131674
2011-05-19 20:55:25 +00:00
1407fb4bbe
Reapply r131605. This time with a fix, which is to use NoFolder.
...
llvm-svn: 131673
2011-05-19 20:52:46 +00:00
0fc5e89c82
ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.
...
Fixes PR9934.
We really need to start tblgening the relocation info :-(
llvm-svn: 131669
2011-05-19 20:32:34 +00:00
9e6a8cca5d
Align i64 arguments to 64 bit boundaries.
...
llvm-svn: 131668
2011-05-19 20:29:48 +00:00
7e6e8951af
Implement the Win64 EH prolog instruction methods on the base MCStreamer.
...
I had to change the API slightly to avoid overloading issues.
llvm-svn: 131666
2011-05-19 19:35:55 +00:00
2b9bd38678
crc32 with 64-bit output zeros upper 32-bits. rdar://9467055
...
llvm-svn: 131664
2011-05-19 18:57:12 +00:00
4a4e5a2b55
Update some currently-disabled code, preparing for eventual use.
...
llvm-svn: 131663
2011-05-19 18:48:20 +00:00
05fd5aa1d0
Increase number of available registers when target is MIPS32.
...
llvm-svn: 131660
2011-05-19 18:25:03 +00:00
dc867ae1fc
Add comment.
...
llvm-svn: 131659
2011-05-19 18:18:39 +00:00
92ab6db6c8
Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic.
...
llvm-svn: 131657
2011-05-19 18:06:05 +00:00
74ba2623ce
Reapply 131644 including the missing header changes:
...
Introduce -fatal-assembler-warnings for the obvious purpose
llvm-svn: 131655
2011-05-19 18:00:13 +00:00
c72240bbd9
Reverting 131641 to investigate 'bot complaint.
...
llvm-svn: 131654
2011-05-19 17:54:42 +00:00
3e2f17499e
Revert r131644; it's breaking the build.
...
llvm-svn: 131653
2011-05-19 17:48:09 +00:00
4cd8856704
Turns out GAS does have Win64 EH directives. (It also supports WinCE EH.) Make
...
ours compatible with GAS.
In retrospect, I should have emailed binutils about this earlier. Thanks to
Kai Tietz for pointing out that GAS already had SEH directives.
llvm-svn: 131652
2011-05-19 17:46:39 +00:00
eca54e4e6d
80 columns.
...
llvm-svn: 131649
2011-05-19 17:34:53 +00:00
59b523169f
Introduce -fatal-assembler-warnings for the obvious purpose
...
llvm-svn: 131644
2011-05-19 17:27:01 +00:00
d1465bd68b
Fix data layout string. i64 is aligned to 64 bit boundaries.
...
llvm-svn: 131642
2011-05-19 17:21:09 +00:00
b476b0cc9f
Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be
...
pseudos. rdar://problem/8614450
llvm-svn: 131641
2011-05-19 16:59:50 +00:00
9eb5a410bd
Use the correct register class for Cell varargs spilling. This fixes all of the
...
verifier failures in the CodeGen/CellSPU tests.
llvm-svn: 131631
2011-05-19 04:44:19 +00:00
6d9e1c7c2e
Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change.
...
llvm-svn: 131630
2011-05-19 04:15:07 +00:00
b4222589bf
Implement the StartChained and EndChained Win64 EH methods on MCStreamer.
...
llvm-svn: 131629
2011-05-19 04:04:13 +00:00
41025dc95b
Make CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll pass with the verifier.
...
llvm-svn: 131627
2011-05-19 03:11:06 +00:00
dadd73390f
Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointless
...
piclabel operand. The operand in the tablegen definition doesn't actually turn
into an MI operand, so it just confuses anything checking the TargetInstrDesc
for the number of operands. It suffices to just have an implicit def of LR.
llvm-svn: 131626
2011-05-19 02:56:28 +00:00
58eafde58b
Reuse the TargetInstrDesc.
...
llvm-svn: 131625
2011-05-19 02:56:23 +00:00
d991ec4e68
Implement the StartProc and EndProc Win64 EH methods on the base MCStreamer.
...
Based largely on Rafael Espindola's work on CFI. Other methods soon to follow.
llvm-svn: 131623
2011-05-19 02:49:00 +00:00
964602d7ba
revert 131605 to fix PR9946.
...
llvm-svn: 131620
2011-05-19 02:26:30 +00:00
00b780e280
Correctly constrain a register class when computing frame offsets, as the Thumb2
...
add instruction takes an rGPR. This fixes the last of PR8825.
llvm-svn: 131619
2011-05-19 02:18:27 +00:00
fe5795a1f6
Revert r128961 because it didn't include a test and causes the verifier to fail
...
on CodeGen/X86/2007-05-07-InvokeSRet.ll. There is probably a bug here that was
fixed by r128961, but since there is no test or reference to a source file I have
to revert it.
llvm-svn: 131618
2011-05-19 01:56:19 +00:00
6efb64ea8e
Make the demanded bits/elements optimizations preserve debug line information.
...
I'm not sure this is quite ideal, but I can't really think of any better way to do it.
llvm-svn: 131616
2011-05-19 01:20:42 +00:00
13733a137c
Avoid a Twine that referenced a tmp (which proceded to go out of scope before
...
the Twine was used).
llvm-svn: 131612
2011-05-19 00:45:05 +00:00
3015a54813
Use IRBuilder.
...
llvm-svn: 131609
2011-05-19 00:13:33 +00:00
31458a0002
Use IRBuilder while simplifying unreachable.
...
llvm-svn: 131607
2011-05-19 00:09:21 +00:00
f1bda7c90c
Revert my previous patch. The cmake build had already been fixed.
...
llvm-svn: 131606
2011-05-19 00:02:45 +00:00
4b13f39b77
Use IRBuilder while simplifying conditional branch.
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llvm-svn: 131605
2011-05-18 23:59:51 +00:00
41e509a33d
More instcombine cleanup, towards improving debug line info.
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llvm-svn: 131604
2011-05-18 23:58:37 +00:00
6bfca4efd8
Restore sanity to 131601.
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llvm-svn: 131603
2011-05-18 23:56:43 +00:00
efbdd80d77
Fix the cmake build.
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llvm-svn: 131602
2011-05-18 23:56:40 +00:00
b098471538
Objective C functions may use a magic '\1' on the name. Handle that when
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dealing with them in the MCJIT.
llvm-svn: 131601
2011-05-18 23:53:21 +00:00
d1b0f0f1b8
Shuffle StandardPasses.cpp into VMCore; add it to CMake.
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llvm-svn: 131600
2011-05-18 23:51:11 +00:00
7de6c4bf75
Use IRBuilder while simplifying branch.
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llvm-svn: 131598
2011-05-18 23:18:47 +00:00
6fc94dd687
Revert unintentional commit.
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llvm-svn: 131597
2011-05-18 23:13:10 +00:00
1754a25977
More instcombine simplifications towards better debug locations.
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llvm-svn: 131596
2011-05-18 23:11:30 +00:00
b9bef106c6
Add missing mayLoad / mayStore flags to instruction definitions without patterns,
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which fixes all of the CodeGen/MBlaze verifier failures.
llvm-svn: 131595
2011-05-18 23:03:10 +00:00
9ddeceff19
Reserve the segment registers on x86 to fix verifier failures in any code that
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uses them.
llvm-svn: 131591
2011-05-18 22:24:48 +00:00
27117af772
Remove comments as Chris requested.
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llvm-svn: 131590
2011-05-18 22:13:51 +00:00
8b2e426555
Reserve r29 on Alpha. This fixes all verifier failures in CodeGen/Alpha.
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llvm-svn: 131587
2011-05-18 21:54:32 +00:00
1d11720ae4
Handle perfect shuffle case that generates a vrev for vectors of floats.
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Add test case.
llvm-svn: 131582
2011-05-18 21:44:54 +00:00
fadb03d6cc
Third pass at allowing plugins to modify default passes. This time with a tweak so that we don't depend on an uninitialized argument.
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llvm-svn: 131581
2011-05-18 21:40:04 +00:00
dd14e0f7fa
Use IRBuilder while simplifying return instruction.
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llvm-svn: 131580
2011-05-18 21:33:11 +00:00
492f87de4e
Fix an obvious typo in r131572.
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llvm-svn: 131579
2011-05-18 21:29:07 +00:00
ec645bf75d
Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on.
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llvm-svn: 131578
2011-05-18 21:25:14 +00:00
3268e4d692
When forming an ICmpZero LSRUse, normalize the non-IV operand
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of the comparison, so that the resulting expression is fully
normalized. This fixes PR9939.
llvm-svn: 131576
2011-05-18 21:02:18 +00:00
77e0610d7c
Add some more Win64 EH directives:
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- StartChained and EndChained delimit a chained unwind area, which can contain
additional operations to be undone if an exception occurs inside of it.
- UnwindOnly declares that this function doesn't handle any exceptions. If it
has a handler, it's an unwind handler instead of an exception handler.
- Lsda declares the location and size of the LSDA, which in the Win64 EH
scheme is kept inside the UNWIND_INFO struct. Windows itself ignores the
LSDA; it's used by the Language-Specific Handler (the "Personality Function"
from DWARF).
llvm-svn: 131572
2011-05-18 20:54:10 +00:00
583805530c
Spread use of IRBuilder even more.
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llvm-svn: 131571
2011-05-18 20:53:17 +00:00
65816ac54d
Revert r131556; it's breaking buildbots/clang tests.
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llvm-svn: 131567
2011-05-18 20:39:27 +00:00
a7ec47d23c
Use IRBuilder while simplifying switch instruction.
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llvm-svn: 131566
2011-05-18 20:35:38 +00:00
071634612d
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
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llvm-svn: 131565
2011-05-18 20:32:41 +00:00
0b373dca1f
Use IRBuilder while simplifying unwind.
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llvm-svn: 131561
2011-05-18 20:01:18 +00:00
f4e832b14e
Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible.
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llvm-svn: 131560
2011-05-18 19:59:50 +00:00
49346010f8
More instcombine cleanup aimed towards improving debug line info.
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llvm-svn: 131559
2011-05-18 19:57:14 +00:00
13c90786e1
Second pass at allowing plugins to modify default passes. This time without bonus inter-library dependencies.
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llvm-svn: 131556
2011-05-18 19:00:41 +00:00
522fbfea3b
Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159.
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llvm-svn: 131555
2011-05-18 18:59:17 +00:00
80632c91b0
Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178
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llvm-svn: 131553
2011-05-18 18:47:27 +00:00
2c2ea226b7
Use IRBuilder while simplifying terminator.
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llvm-svn: 131552
2011-05-18 18:43:31 +00:00
767f6930bc
Use IRBuilder while simplifying unconditional branch.
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llvm-svn: 131551
2011-05-18 18:28:48 +00:00
5c810ce4a3
Use IRBuilder while folding two entry PHINode.
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llvm-svn: 131548
2011-05-18 18:16:44 +00:00
2fd66441c6
Switch more inst insertion in instcombine to IRBuilder.
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llvm-svn: 131547
2011-05-18 18:10:28 +00:00
15ad6761da
Set up IRBuilder for use during simplification.
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llvm-svn: 131545
2011-05-18 18:01:27 +00:00
0b43b9ee98
Switch more inst insertion in instcombine to IRBuilder.
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llvm-svn: 131544
2011-05-18 17:58:37 +00:00
8fa6ebf975
fix typo
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llvm-svn: 131543
2011-05-18 17:37:10 +00:00
cde9c1628c
Switch inst insertion in instcombine transform to IRBuilder.
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llvm-svn: 131542
2011-05-18 17:31:55 +00:00
1fabbe921b
Use IRBuiler while constant folding terminator.
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llvm-svn: 131541
2011-05-18 17:26:46 +00:00
728f6260b9
Fix inelegant initialization.
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llvm-svn: 131538
2011-05-18 15:54:26 +00:00
bbdcd17d44
PTX: add flag to disable mad/fma selection
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Patch by Dan Bailey
llvm-svn: 131537
2011-05-18 15:42:23 +00:00
3d9407f4eb
Revert commit 131534 since it seems to have broken several buildbots.
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Original log entry:
Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'
code in one place.
llvm-svn: 131536
2011-05-18 14:57:56 +00:00
c5c27ede55
Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'
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code in one place.
llvm-svn: 131534
2011-05-18 12:26:38 +00:00
27bd0df352
Now that SrcBits and DestBits always represent the primitive size, rather
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than either the primitive size or the element primitive size (in the case
of vectors), simplify the vector logic. No functionality change. There
is some distracting churn in the patch because I lined up comments better
while there - sorry about that.
llvm-svn: 131533
2011-05-18 10:59:25 +00:00
7f64656d21
Tighten up checking of the validity of casts. (1) The IR parser would
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happily accept things like "sext <2 x i32> to <999 x i64>". It would
also accept "sext <2 x i32> to i64", though the verifier would catch
that later. Fixed by having castIsValid check that vector lengths match
except when doing a bitcast. (2) When creating a cast instruction, check
that the cast is valid (this was already done when creating constexpr
casts). While there, replace getScalarSizeInBits (used to allow more
vector casts) with getPrimitiveSizeInBits in getCastOpcode and isCastable
since vector to vector casts are now handled explicitly by passing to the
element types; i.e. this bit should result in no functional change.
llvm-svn: 131532
2011-05-18 09:21:57 +00:00
a8514535a4
Teach getCastOpcode about element-by-element vector casts. For example, "trunc"
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can be used to turn a <4 x i64> into a <4 x i32> but getCastOpcode would assert
if you passed these types to it. Note that this strictly extends the previous
functionality: if getCastOpcode previously accepted two vector types (i.e. didn't
assert) then it still will and returns the same opcode (BitCast). That's because
before it would only accept vectors with the same bitwidth, and the new code only
touches vectors with the same length. However if two vectors have both the same
bitwidth and the same length then their element types have the same bitwidth, so
the new logic will return BitCast as before.
llvm-svn: 131530
2011-05-18 07:13:41 +00:00
48b182c3a4
In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
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Updated test case and reverted change to the PerfectShuffle Table.
llvm-svn: 131529
2011-05-18 06:42:21 +00:00
8d9c99042f
Implement the Win64 EH directive methods for the assembly language streamer.
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GAS has no such directives (not even mingw-w64 GAS has them), so I took
creative license with their names in assembly. I prefixed them all with
"w64_" to avoid namespace collisions, for example. If I discover that GAS
has taken a different approach, I'll change ours to match.
llvm-svn: 131525
2011-05-18 04:58:05 +00:00
07b5c276f4
Eliminate dead dead code elimination code.
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llvm-svn: 131524
2011-05-18 04:51:15 +00:00
f3dc225972
Also use shrinkToUses after AdjustCopiesBackFrom().
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The 'last use' may not be in the same basic block, and we still want a correct
live range.
llvm-svn: 131523
2011-05-18 04:51:12 +00:00
384041d0dc
While thinking about how to know where the functions' boundaries are for
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the purposes of the Win64 EH tables, I realized we had no way to tell where
the function ends. (MASM bounds functions with PROC and ENDP keywords.)
Add a directive to delimit the end of the function, and rename the 'frame'
directive to more accurately reflect its duality with the new directive.
llvm-svn: 131522
2011-05-18 04:47:22 +00:00
595a47d462
Properly shrink live ranges after deleting dead copies. Clean up after all joined copies.
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LiveInterval::shrinkToUses recomputes the live range from scratch instead of
removing snippets. This should avoid the problem with dangling live ranges.
Leave physreg identity copies alone. They can be created when joining a virtreg
with a physreg. They don't affect register allocation, and they will be removed
by the rewriter.
llvm-svn: 131521
2011-05-18 04:18:19 +00:00
f9839e4257
Fix typo.
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llvm-svn: 131519
2011-05-18 02:29:50 +00:00
d7c55fe2ef
Fix more of PR8825 by correctly using rGPR registers when lowering atomic
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compare-and-swap intrinsics.
llvm-svn: 131518
2011-05-18 02:20:07 +00:00
96254a0d53
Start trying to make InstCombine preserve more debug info. The idea here is to set the debug location on the IRBuilder, which will be then right location in most cases. This should magically give many transformations debug locations, and fixing places which are missing a debug location will usually just means changing the code creating it to use the IRBuilder.
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As an example, the change to InstCombineCalls catches a common case where a call to a bitcast of a function is rewritten.
Chris, does this approach look reasonable?
llvm-svn: 131516
2011-05-18 01:28:27 +00:00
b9ed18f2cb
Use ReplaceInstUsesWith instead of replaceAllUsesWith where appropriate in instcombine.
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llvm-svn: 131512
2011-05-18 00:32:01 +00:00
b849cd511b
Preseve line numbers while simplifying CFG.
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llvm-svn: 131508
2011-05-17 23:29:05 +00:00
33a67ddbd2
Actually, the address operand of the Thumb2 LDREX / STREX instructions *can*
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take r13, so we can just make it a GPR. This fixes PR8825.
llvm-svn: 131507
2011-05-17 23:26:20 +00:00
c5d272766f
Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They
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were marked as taking a tGPR when in reality they take an rGPR.
llvm-svn: 131506
2011-05-17 23:11:12 +00:00
0671ba8448
Conditionalize the format of the GCOV files by target type. Darwin uses the 4.2
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format.
llvm-svn: 131503
2011-05-17 23:05:13 +00:00
e9692808b7
Make fast-isel miss counting in -stats and -fast-isel-verbose take terminators into account; since there are many fewer isel misses with recent changes, misses caused by terminators are more significant.
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llvm-svn: 131502
2011-05-17 23:02:10 +00:00
abffc991dc
Misc. code cleanups.
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llvm-svn: 131497
2011-05-17 22:22:52 +00:00
4298df6d86
Misc. code cleanups.
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llvm-svn: 131495
2011-05-17 22:20:36 +00:00
5bd18b6638
X86 pmovsx/pmovzx ignore the upper half of their inputs.
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rdar://problem/6945110
llvm-svn: 131493
2011-05-17 22:13:31 +00:00
c7e291b354
vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.
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llvm-svn: 131488
2011-05-17 20:48:40 +00:00
341b38c22a
Preserve line number information.
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llvm-svn: 131482
2011-05-17 20:00:02 +00:00
c5933f2418
Set debug loc for new load instruction.
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llvm-svn: 131481
2011-05-17 19:43:38 +00:00
c23bcbc498
Preserve line number information.
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llvm-svn: 131480
2011-05-17 19:43:06 +00:00
6f6b44d19d
Enable autodetect of popcnt
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llvm-svn: 131476
2011-05-17 18:33:37 +00:00
7b27942fe7
Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872.
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This is r131438 with a couple small fixes.
llvm-svn: 131474
2011-05-17 18:29:03 +00:00
d000a2c26e
Clean up the mess created by r131467+r131469.
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llvm-svn: 131471
2011-05-17 18:02:22 +00:00
c65d8eda7b
Revert 131467 due to buildbot complaint.
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llvm-svn: 131469
2011-05-17 16:59:46 +00:00
3cf5308890
Fix an obscure issue in X86_64 parameter passing: if a tiny byval is
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passed as the fifth parameter, insure it's passed correctly (in R9).
rdar://problem/6920088
llvm-svn: 131467
2011-05-17 16:45:55 +00:00
52375e6a01
Tweak cross-class coalescing to be more aggressive when the target class is small.
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The greedy register allocator has live range splitting and register class
inflation, so it can actually fully undo this join, including restoring the
original register classes.
We still don't want to do this for long live ranges, mostly because of the high
register pressure of there are many constrained live ranges overlapping.
llvm-svn: 131466
2011-05-17 16:38:37 +00:00
0693182265
Don't include information about the build into the information returned by
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getHostTriple. This fixes a 32 bit clang running on a 64 bit ubuntu.
llvm-svn: 131463
2011-05-17 15:26:34 +00:00
d8edb1d5cc
Fix a bug in PerformEXTRACT_VECTOR_ELTCombine. The code created an ADD SDNode
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with two different types, in cases where the index and the ptr had different
types.
llvm-svn: 131461
2011-05-17 08:31:57 +00:00
56a42ebf15
Update comment.
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llvm-svn: 131459
2011-05-17 08:16:14 +00:00
a1d9e29552
Support XOR and AND optimization with no return value.
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Finishes off rdar://8470697
llvm-svn: 131458
2011-05-17 08:10:18 +00:00
abfe3131e3
Couple less magic numbers.
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llvm-svn: 131457
2011-05-17 07:50:41 +00:00
eb47a2a1e5
Make this code a little less magic number laden.
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llvm-svn: 131456
2011-05-17 07:47:55 +00:00
1e81f57bf0
add a note
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llvm-svn: 131455
2011-05-17 07:22:33 +00:00
7335e8a720
Back out r131444 and r131438; they're breaking nightly tests. I'll look into
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it more tomorrow.
llvm-svn: 131451
2011-05-17 02:36:59 +00:00
83ba150f3a
Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872.
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llvm-svn: 131438
2011-05-17 00:13:47 +00:00
97f0cf32ea
@llvm.lifetime.begin acts as a load, not @llvm.lifetime.end.
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llvm-svn: 131437
2011-05-17 00:05:49 +00:00
4edf17d91f
Teach LiveInterval::isZeroLength about null SlotIndexes.
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When instructions are deleted, they leave tombstone SlotIndex entries.
The isZeroLength method should ignore these null indexes.
This causes RABasic to sometimes spill a callee-saved register in the
abi-isel.ll test, so don't run that test with -regalloc=basic. Prioritizing
register allocation according to spill weight can cause more registers to be
used.
llvm-svn: 131436
2011-05-16 23:50:05 +00:00
4e983166bc
Kill some dead code.
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llvm-svn: 131431
2011-05-16 22:24:07 +00:00
d282f46c6b
Delete unused variables.
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llvm-svn: 131430
2011-05-16 22:19:54 +00:00
d4d12d14b5
Trim #includes.
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llvm-svn: 131429
2011-05-16 22:14:50 +00:00
ae9b1685a8
Fix whitespace and 80-column violations.
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llvm-svn: 131428
2011-05-16 22:09:53 +00:00
a0b682db62
There is no need to force DebugLoc on a PHI at this point.
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llvm-svn: 131427
2011-05-16 22:05:03 +00:00
e85c0dde7a
Track how many insns fast-isel successfully selects as well as how many it
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misses.
llvm-svn: 131426
2011-05-16 21:51:07 +00:00
d4a3609d30
Remove dead code. Fix associated test to use FileCheck.
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llvm-svn: 131424
2011-05-16 21:28:22 +00:00
8e60ff11db
Preserve debug info for unused zero extended boolean argument.
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Radar 9422775.
llvm-svn: 131422
2011-05-16 21:24:05 +00:00
2701815ed8
Add a method I forgot in the last commit. Don't worry, this one passed
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self-host :).
llvm-svn: 131421
2011-05-16 21:13:58 +00:00
a4d4a0162d
Make fast-isel work correctly s/uadd.with.overflow intrinsics.
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llvm-svn: 131420
2011-05-16 21:06:17 +00:00
Renato Golin