Commit Graph

18442 Commits

Author SHA1 Message Date
Arnaud A. de Grandmaison 61c167c62b Teach InstCombine to work with smaller legal types in icmp (shl %v, C1), C2
It enables to work with a smaller constant, which is target friendly for those which can compare to immediates.
It also avoids inserting a shift in favor of a trunc, which can be free on some targets.

This used to work until LLVM-3.1, but regressed with the 3.2 release.

llvm-svn: 175270
2013-02-15 14:35:47 +00:00
Kostya Serebryany a968568165 [asan] support long double on 64-bit. See https://code.google.com/p/address-sanitizer/issues/detail?id=151
llvm-svn: 175266
2013-02-15 12:46:06 +00:00
Tim Northover 3533ad6bbd AArch64: remove ConstantIsland pass & put literals in separate section.
This implements the review suggestion to simplify the AArch64 backend. If we
later discover that we *really* need the extra complexity of the
ConstantIslands pass for performance reasons it can be resurrected.

llvm-svn: 175258
2013-02-15 09:33:43 +00:00
Tim Northover 5466e36fb5 AArch64: refactor frame handling to use movz/movk for overlarge offsets.
In the near future litpools will be in a different section, which means that
any access to them is at least two instructions. This makes the case for a
movz/movk pair (if total offset <= 32-bits) even more compelling.

llvm-svn: 175257
2013-02-15 09:33:26 +00:00
Bill Wendling 26b95756c1 Simplify the 'operator<' for the attribute object.
llvm-svn: 175252
2013-02-15 05:25:26 +00:00
Anna Zaks 269d1fa991 Revert "Fix testcase for attribute ordering."
This reverts commit 58f20a3cbfca7384fe5e25e095f18572736a4792.

llvm-svn: 175249
2013-02-15 04:15:53 +00:00
Anna Zaks 61040b915d Revert "Fix testcase for attribute ordering."
This reverts commit 997c6516ca161073a1d516ebca7c0ca7722f64e2.

llvm-svn: 175248
2013-02-15 04:15:50 +00:00
Bill Wendling f7d8d767fb Fix testcase for attribute ordering.
llvm-svn: 175238
2013-02-15 01:04:46 +00:00
Reed Kotler f022147790 Fix minor mips16 issues in directives for function prologue. Probably this does
not matter but makes it more gcc compatible which avoids possible subtle
problems. Also, turned back on a disabled check in helloworld.ll. 

llvm-svn: 175237
2013-02-15 01:04:38 +00:00
Bill Wendling fa1d248ccf Fix testcase for attribute ordering.
llvm-svn: 175236
2013-02-15 00:58:25 +00:00
Joel Jones 0f8617b17e The ARM NEON vector compare instructions take three arguments. However, the
assembler should also accept a two arg form, as the docuemntation specifies that
the first (destination) register is optional.

This patch uses TwoOperandAliasConstraint to add the two argument form.

It also fixes an 80-column formatting problem in:
  test/MC/ARM/neon-bitwise-encoding

<rdar://problem/12909419> Clang rejects ARM NEON assembly instructions

llvm-svn: 175221
2013-02-14 23:18:40 +00:00
Kay Tiong Khoo 7b564da474 death to extra whitespace
llvm-svn: 175200
2013-02-14 19:15:14 +00:00
Kay Tiong Khoo f809c6491d added basic support for Intel ADX instructions
-feature flag, instructions definitions, test cases

llvm-svn: 175196
2013-02-14 19:08:21 +00:00
Nadav Rotem 495b1a43c1 Dont merge consecutive loads/stores into vectors when noimplicitfloat is used.
llvm-svn: 175190
2013-02-14 18:28:52 +00:00
Weiming Zhao c598700788 Re-apply r175088 for bug fix 13622: Add paired register support for
inline asm with 64-bit data on ARM

Update test case to use -mtriple=arm-linux-gnueabi

llvm-svn: 175186
2013-02-14 18:10:21 +00:00
Vincent Lejeune f940fd05bd R600: Do not fold single instruction with more that 3 kcache read
It fixes around 100 tfb piglit tests and 16 glean tests.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175183
2013-02-14 16:57:19 +00:00
Rafael Espindola 86d5345988 Revert r15266. This fixes llvm.org/pr15266.
llvm-svn: 175173
2013-02-14 16:23:08 +00:00
Krzysztof Parzyszek f71a69d608 Add testcase for llvm-dwarfdump to test parsing of the pubnames data.
llvm-svn: 175168
2013-02-14 16:10:58 +00:00
Kristof Beyls 2efb59a719 Make ARMAsmParser accept the correct alignment specifier syntax in instructions.
The parser will now accept instructions with alignment specifiers written like
    vld1.8  {d16}, [r0:64]
, while also still accepting the incorrect syntax
    vld1.8  {d16}, [r0, :64]

llvm-svn: 175164
2013-02-14 14:46:12 +00:00
Elena Demikhovsky 5b9d426907 Moved line-info.ll to DebugInfo\X86 directory
llvm-svn: 175150
2013-02-14 09:07:34 +00:00
Elena Demikhovsky 70247a807b The test failed on Windows. I've changed the platform to run to "x86_64-apple-darwin".
llvm-svn: 175146
2013-02-14 08:23:08 +00:00
Elena Demikhovsky d0a0cc80cd Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).
Added a test.

llvm-svn: 175144
2013-02-14 08:20:26 +00:00
Michel Danzer 51d5eb2f63 R600: Add lit tests for texture sampling instruction selection.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175138
2013-02-14 07:43:51 +00:00
Andrew Trick 6871e5f4e5 Reapply "s/grep/FileCheck/ in some tests"
This reverts commit fd1335e982bbf93c5f450ed4fd29f9f787435c85.

Use a triple this time.

llvm-svn: 175134
2013-02-14 03:45:08 +00:00
Nick Lewycky 06417743cf Teach the DataLayout aware constant folder to be much more aggressive towards
'and' instructions. This is a pattern that shows up a lot in ubsan binaries.

llvm-svn: 175128
2013-02-14 03:23:37 +00:00
Andrew Trick 836bf1526b Revert "s/grep/FileCheck/ in some tests"
This reverts commit 8b75e6bc35fb3f9c1e788dbd05084c0f4a60a0f3.

The FileCheck tests are not equivalent:

test/CodeGen/X86/tailcall-structret.ll:6:10: error: expected string not found in input
; CHECK: jmp init
         ^
<stdin>:1:2: note: scanning from here
 .section __TEXT,__text,regular,pure_instructions
 ^
<stdin>:13:2: note: possible intended match here
 jmp _init ## TAILCALL
 ^

llvm-svn: 175124
2013-02-14 03:00:57 +00:00
Weiming Zhao 090edf7e67 temporarily revert the patch due to some conflicts
llvm-svn: 175107
2013-02-13 23:24:40 +00:00
Anshuman Dasgupta e96f804eba Hexagon: add support for predicate-GPR copies.
llvm-svn: 175102
2013-02-13 22:56:34 +00:00
Tom Stellard 91da4e9199 R600: Add support for 128-bit parameters
NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175096
2013-02-13 22:05:20 +00:00
Eli Bendersky 3ffeb68dd7 s/grep/FileCheck/ in some tests
llvm-svn: 175093
2013-02-13 22:00:37 +00:00
Eli Bendersky 04553985d7 s/grep/FileCheck/ in some tests
llvm-svn: 175089
2013-02-13 21:46:38 +00:00
Weiming Zhao 0632a4b002 Bug fix 13622: Add paired register support for inline asm with 64-bit data on ARM
llvm-svn: 175088
2013-02-13 21:43:02 +00:00
Chad Rosier da05cf7ba7 [ms-inline asm] Fix up test case for non-Darwin platforms.
llvm-svn: 175087
2013-02-13 21:41:58 +00:00
Jyotsna Verma d92252469e Hexagon: Use absolute addressing mode loads/stores for global+offset
instead of redefining separate instructions for them.

llvm-svn: 175086
2013-02-13 21:38:46 +00:00
Chad Rosier 282edd7caa [ms-inline-asm] Add support for memory references that have non-immediate
displacements.
rdar://12974533

llvm-svn: 175083
2013-02-13 21:33:44 +00:00
Reed Kotler f662cff689 For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.

llvm-svn: 175073
2013-02-13 20:28:27 +00:00
Manman Ren 7a4c8a783c Clean up LDV, no functionality change.
Remove dead functions: renameRegister
Move private member variables from LDV to Impl
Remove ssp/uwtable from testing case

llvm-svn: 175072
2013-02-13 20:23:48 +00:00
David Peixotto 6eecb28d3a PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA
Fixed bug in tablegen conversion when source pseudo instruction has
a different number of arguments than the destination instruction.

llvm-svn: 175066
2013-02-13 19:21:47 +00:00
Benjamin Kramer 8e2637e2b0 X86: Disable generation of rep;movsl when %esi is used as a base pointer.
This happens when there is both stack realignment and a dynamic alloca in the
function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the
base pointer and the next register spill will write into oblivion.

Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas
and freebsd a 4 byte stack alignment.

llvm-svn: 175057
2013-02-13 13:40:35 +00:00
Reed Kotler 9cb8e7b9f5 Make jumptables work for -static
llvm-svn: 175044
2013-02-13 08:32:14 +00:00
Elena Demikhovsky 9e0df7cb01 Prevent insertion of "vzeroupper" before call that preserves YMM registers, since a caller uses preserved registers across the call.
llvm-svn: 175043
2013-02-13 08:02:04 +00:00
Eric Christopher 389ee71b0a Check i1 as well as i8 variables for 8 bit registers for x86 inline
assembly.

llvm-svn: 175036
2013-02-13 06:01:05 +00:00
Eric Christopher 2398a9a175 Finish obviously broken thought.
llvm-svn: 175035
2013-02-13 06:01:00 +00:00
Kostya Serebryany 3838f27905 [tsan] disable load widening in ThreadSanitizer mode
llvm-svn: 175034
2013-02-13 05:59:45 +00:00
Manman Ren f019cd62da Debug Info: LiveDebugVarible can remove DBG_VALUEs, make sure we emit them back.
RegisterCoalescer used to depend on LiveDebugVariable. LDV removes DBG_VALUEs
without emitting them at the end.

We fix this by removing LDV from RegisterCoalescer. Also add an assertion to
make sure we call emitDebugValues if DBG_VALUEs are removed at
runOnMachineFunction.

rdar://problem/13183203
Reviewed by Andy & Jakob

llvm-svn: 175023
2013-02-13 01:14:49 +00:00
Krzysztof Parzyszek 5974de4e7d Remove target-specific info from the testcase for DWARF/pubnames.
llvm-svn: 174992
2013-02-12 18:53:21 +00:00
Chad Rosier f72d06a919 [ms-inline asm] Add support for lexing binary integers with a [bB] suffix.
This is complicated by backward labels (e.g., 0b can be both a backward label
and a binary zero).  The current implementation assumes [0-9]b is always a
label and thus it's possible for 0b and 1b to not be interpreted correctly for
ms-style inline assembly.  However, this is relatively simple to fix in the
inline assembly (i.e., drop the [bB]).

This patch also limits backward labels to [0-9]b, so that only 0b and 1b are
ambiguous.
Part of rdar://12470373

llvm-svn: 174983
2013-02-12 18:29:02 +00:00
Krzysztof Parzyszek 228daa6986 Allow optionally generating pubnames section in DWARF info. Introduce
option "generate-dwarf-pubnames" to control it, set to "false" by default.

llvm-svn: 174981
2013-02-12 18:00:14 +00:00
Kay Tiong Khoo c5c9713fcf added test cases for r174920 (prefetch disassembly)
llvm-svn: 174979
2013-02-12 17:07:44 +00:00
Paul Redmond 7e7e3de43d Fix the lit test added in r174972
Patch by: Kevin Schoedel

llvm-svn: 174974
2013-02-12 16:07:27 +00:00
Jyotsna Verma 39f7a2b7a0 Hexagon: Add support to generate predicated absolute addressing mode
instructions.

llvm-svn: 174973
2013-02-12 16:06:23 +00:00
Paul Redmond 288604ed0c PR14562 - Truncation of left shift became undef
DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32))
into (shl i32 v, 32) into undef. To prevent this, check the shift count
against the final result size.

Patch by: Kevin Schoedel
Reviewed by: Nadav Rotem

llvm-svn: 174972
2013-02-12 15:21:21 +00:00
Justin Holewinski be8dc6499a [NVPTX] Disable vector registers
Vectors were being manually scalarized by the backend.  Instead,
let the target-independent code do all of the work.  The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.

llvm-svn: 174968
2013-02-12 14:18:49 +00:00
Kostya Serebryany e2e32b32e8 [asan] fix tests for the new ABI
llvm-svn: 174959
2013-02-12 11:14:24 +00:00
Bill Wendling 7321fec934 Test for string attributes and for attribute group output.
llvm-svn: 174954
2013-02-12 09:14:20 +00:00
Arnold Schwaighofer 89aef93841 ARM cost model: Add vector reverse shuffle costs
A reverse shuffle is lowered to a vrev and possibly a vext instruction (quad
word).

radar://13171406

llvm-svn: 174933
2013-02-12 02:40:39 +00:00
Arnold Schwaighofer 1f3d3ca769 ARM NEON: Handle v16i8 and v8i16 reverse shuffles
Lower reverse shuffles to a vrev64 and a vext instruction instead of the default
legalization of storing and loading to the stack. This is important because we
generate reverse shuffles in the loop vectorizer when we reverse store to an
array.

  uint8_t Arr[N];
  for (i = 0; i < N; ++i)
    Arr[N - i - 1] = ...

radar://13171760

llvm-svn: 174929
2013-02-12 01:58:32 +00:00
Chad Rosier 8bc655605b [ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.
Part of rdar://12470373

llvm-svn: 174926
2013-02-12 01:00:01 +00:00
Michael Ilseman 74a6da963b Optimization: bitcast (<1 x ...> insertelement ..., X, ...) to ... ==> bitcast X to ...
llvm-svn: 174905
2013-02-11 21:41:44 +00:00
Krzysztof Parzyszek 9a278f108a Extend Hexagon hardware loop generation to handle various additional cases:
- variety of compare instructions,
- loops with no preheader,
- arbitrary lower and upper bounds.

llvm-svn: 174904
2013-02-11 21:37:55 +00:00
Michael Ilseman 35f82ff833 Remove trailing whitespace
llvm-svn: 174903
2013-02-11 21:36:49 +00:00
Kay Tiong Khoo d30b1a2ac7 *fixed disassembly of some i386 system insts with intel syntax
*added file for test cases for i386 intel syntax

llvm-svn: 174900
2013-02-11 19:46:36 +00:00
Justin Holewinski 4f12f53353 [NVPTX] Remove NoCapture from address space conversion intrinsics. NoCapture is not valid in this case, and was causing incorrect optimizations.
llvm-svn: 174896
2013-02-11 18:56:35 +00:00
Tim Northover 09995ac069 AArch64: generate dwarfdump test rather than include .o in subversion
llvm-svn: 174891
2013-02-11 16:28:12 +00:00
Tim Northover acaa788be6 AArch64: Add basic relocation processing for llvm-dwarfdump.
This allows llvm-dwarfdump to handle the relocations needed, at least
for LLVM-produced code.

llvm-svn: 174874
2013-02-11 11:16:02 +00:00
Tim Northover 45a0d77c48 AArch64: Undo change to how test was run
This broke on Windows, presumably due to interleaving of output streams.

llvm-svn: 174873
2013-02-11 10:51:41 +00:00
Tim Northover 60baeb984f Make use of DiagnosticType to provide better AArch64 diagnostics.
This gives a DiagnosticType to all AsmOperands in sight. This replaces all
"invalid operand" diagnostics with something more specific. The messages given
should still be sufficiently vague that they're not usually actively misleading
when LLVM guesses your instruction incorrectly.

llvm-svn: 174871
2013-02-11 09:29:37 +00:00
Bill Wendling 84ba97698e FileCheck-ize the tests.
llvm-svn: 174865
2013-02-11 08:34:57 +00:00
Kostya Serebryany d688bab563 [tsan/msan] adding thread_safety and uninitialized_checks attributes
llvm-svn: 174864
2013-02-11 08:13:54 +00:00
Andrew Trick bc7059032b LSR IVChain improvement.
Handle chains in which the same offset is used for both loads and
stores to the same array.

Fixes rdar://11410078.

llvm-svn: 174789
2013-02-09 01:11:01 +00:00
Manman Ren d2c95eb995 Dwarf: do not use line_table_start in at_stmt_list since we do not always emit
line table entries in assembly.

llvm-svn: 174785
2013-02-09 00:41:44 +00:00
Reed Kotler b9bf8dca47 Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are the
same so we put in the comment field an indicator when we think we are
emitting the 16 bit version. For the direct object emitter, the difference is 
important as well as for other passes which need an accurate count of 
program size. There will be other similar putbacks to this for various
instructions.

llvm-svn: 174747
2013-02-08 21:42:56 +00:00
Hal Finkel 2581905f81 DAGCombiner: Constant folding around pre-increment loads/stores
Previously, even when a pre-increment load or store was generated,
we often needed to keep a copy of the original base register for use
with other offsets. If all of these offsets are constants (including
the offset which was combined into the addressing mode), then this is
clearly unnecessary. This change adjusts these other offsets to use the
new incremented address.

llvm-svn: 174746
2013-02-08 21:35:47 +00:00
Bob Wilson 67bbf3aa0c Revert 172027 and 174336. Remove diagnostics about over-aligned stack objects.
Aside from the question of whether we report a warning or an error when we
can't satisfy a requested stack object alignment, the current implementation
of this is not good.  We're not providing any source location in the diagnostics
and the current warning is not connected to any warning group so you can't
control it.  We could improve the source location somewhat, but we can do a
much better job if this check is implemented in the front-end, so let's do that
instead.  <rdar://problem/13127907>

llvm-svn: 174741
2013-02-08 20:35:15 +00:00
Bill Schmidt 62fe7a5b17 Refine fix to bug 15041.
Thanks to help from Nadav and Hal, I have a more reasonable (and even
correct!) approach.  This specifically penalizes the insertelement
and extractelement operations for the performance hit that will occur
on PowerPC processors.

llvm-svn: 174725
2013-02-08 18:19:17 +00:00
Chad Rosier 22d275f7b8 [SimplifyLibCalls] Library call simplification doen't work if the call site
isn't using the default calling convention.  However, if the transformation is
from a call to inline IR, then the calling convention doesn't matter.
rdar://13157990

llvm-svn: 174724
2013-02-08 18:00:14 +00:00
Arnold Schwaighofer 594fa2dc2b ARM cost model: Address computation in vector mem ops not free
Adds a function to target transform info to query for the cost of address
computation. The cost model analysis pass now also queries this interface.
The code in LoopVectorize adds the cost of address computation as part of the
memory instruction cost calculation. Only there, we know whether the instruction
will be scalarized or not.
Increase the penality for inserting in to D registers on swift. This becomes
necessary because we now always assume that address computation has a cost and
three is a closer value to the architecture.

radar://13097204

llvm-svn: 174713
2013-02-08 14:50:48 +00:00
Alexey Samsonov 897f2cf408 Update tests for DWARF parser: store sources next to pre-built object files and provide build instructions
llvm-svn: 174711
2013-02-08 14:34:33 +00:00
Reed Kotler 66165c8f96 When Mips16 frames grow large, the immediate field may exceed the maximum
allowed size for the instruction. This code uses RegScavenger to fix this.
We sometimes need 2 registers for Mips16 so we must handle things
differently than how register scavenger is normally used.

llvm-svn: 174696
2013-02-08 03:57:41 +00:00
Andrew Trick 1bd53c3675 Revert "Have InstCombine call SipmlifyCall when handling calls. Test case included."
This reverts commit 3854a5d90fee52af1065edbed34521fff6cdc18d.

This causes a clang unit test to hang: vtable-available-externally.cpp.

llvm-svn: 174692
2013-02-08 01:55:39 +00:00
Michael Ilseman 6092dc5455 Have InstCombine call SipmlifyCall when handling calls. Test case included.
llvm-svn: 174675
2013-02-07 23:01:35 +00:00
Akira Hatanaka 061d1ea5da [mips] Add definition of JALR instruction which has two register operands. Change the
original JALR instruction with one register operand to be a pseudo-instruction.

llvm-svn: 174657
2013-02-07 19:48:00 +00:00
Michael Ilseman 5485729b9a Identify and simplify idempotent intrinsics. Test case included.
llvm-svn: 174650
2013-02-07 19:26:05 +00:00
Michael J. Spencer 3a967eac1e [Object][ELF] Fix crash on no dynamic section.
llvm-svn: 174639
2013-02-07 18:26:45 +00:00
Arnold Schwaighofer 213fced704 ARM cost model: Add costs for vector selects
Vector selects are cheap on NEON. They get lowered to a vbsl instruction.

radar://13158753

llvm-svn: 174631
2013-02-07 16:10:15 +00:00
Tom Stellard e06163a9a6 R600: Add support for SET*_DX10 instructions
These instructions compare two floating point values and return an
integer true (-1) or false (0) value.

When compiling code generated by the Mesa GLSL frontend, the SET*_DX10
instructions save us four instructions for most branch decisions that
use floating-point comparisons.

llvm-svn: 174609
2013-02-07 14:02:35 +00:00
Tom Stellard 6d867e8d4d R600: Add tests for unsupported condition codes.
All of the le and lt variants are unsupported.

llvm-svn: 174608
2013-02-07 14:02:33 +00:00
Tom Stellard b40ada9b85 R600: Fix assembly name for SETGT_INT
llvm-svn: 174607
2013-02-07 14:02:27 +00:00
Owen Anderson bfd2ce96c7 Remove this testcase until I can figure out how to properly conditionalize it.
llvm-svn: 174591
2013-02-07 07:01:54 +00:00
Owen Anderson 589baf98b4 Another attempt at getting the XFAIL line right for this test.
llvm-svn: 174588
2013-02-07 06:26:55 +00:00
Reed Kotler 4a230ffa96 Make sure we call externals from libraries properly when -static.
For example, when we are doing mips16 hard float or soft float.

llvm-svn: 174583
2013-02-07 04:34:51 +00:00
Reed Kotler ec60f7d335 Enable jumps when in -static mode.
llvm-svn: 174580
2013-02-07 03:49:51 +00:00
Michael Ilseman 1dd6f2a5ba Preserve fast-math flags after reassociation and commutation. Update test cases
llvm-svn: 174571
2013-02-07 01:40:15 +00:00
Michael Ilseman 10f2055812 whitespace
llvm-svn: 174569
2013-02-07 01:27:13 +00:00
Owen Anderson 389f7dc7a2 Fix CMake detection of various cmath functions, and XFAIL the test on platforms that are known to be missing them.
llvm-svn: 174564
2013-02-07 00:54:05 +00:00
Owen Anderson d4ebfd8400 Signficantly generalize our ability to constant fold floating point intrinsics, including ones on half types.
llvm-svn: 174555
2013-02-06 22:43:31 +00:00
Eli Bendersky d5d4c89bf0 Fix typo
llvm-svn: 174553
2013-02-06 22:34:46 +00:00
Eli Bendersky 9fcfe1ed89 Add a comment to the test that points to the source from which the input object
file was generated.

llvm-svn: 174551
2013-02-06 22:17:40 +00:00
Eli Bendersky c0d905c0e9 Add a test for checking the current .debug_frame dumping capability.
The test is a binary placed in test/DebugInfo/Inputs, with a source C
file used for reference/reproducing. The source's first line is a clang
build command for reproducing the binary.

llvm-svn: 174543
2013-02-06 20:55:06 +00:00
Eli Bendersky ef4558abd3 This is a follow-up on r174446, now taking Atom processors into
account. Atoms use LEA for updating SP in prologs/epilogs, and the
exact LEA opcode depends on the data model.

Also reapplying the test case which was added and then reverted
(because of Atom failures), this time specifying explicitly the CPU in
addition to the triple. The test case now checks all variations (data
mode, cpu Atom vs. Core).

llvm-svn: 174542
2013-02-06 20:43:57 +00:00
Guy Benyei 5ea04c385f Canonicalize line endings to Linux style also when the --strict-whitespace flag is in use. This flag is supposed to affect horizontal whitespaces only.
llvm-svn: 174541
2013-02-06 20:40:38 +00:00
Tim Northover 228d9d3aa2 Implement external weak (ELF) symbols on AArch64
Weakly defined symbols should evaluate to 0 if they're undefined at
link-time. This is impossible to do with the usual address generation
patterns, so we should use a literal pool entry to materlialise the
address.

llvm-svn: 174518
2013-02-06 16:43:33 +00:00
Tim Northover a80c4c1a08 Add AArch64 CRC32 instructions
These instructions are a late addition to the architecture, and may
yet end up behind an optional attribute, but for now they're available
at all times.

llvm-svn: 174496
2013-02-06 09:13:13 +00:00
Tim Northover 91a51c5a7c Add icache prefetch operations to AArch64
This adds hints to the various "prfm" instructions so that they can
affect the instruction cache as well as the data cache.

llvm-svn: 174495
2013-02-06 09:04:56 +00:00
Eli Bendersky c4446856e3 Remove this test in the meantime, since it won't pass on Atom. Atom uses lea
to move the stack pointer in prologs/epilogs. I will fix the test and add it
back later.

llvm-svn: 174484
2013-02-06 03:15:00 +00:00
Manman Ren d2c38d684a Attempt to recover gdb bot after r174445.
Failure: undefined symbol 'Lline_table_start0'.
Root-cause: we use a symbol subtraction to calculate at_stmt_list, but
the line table entries are not dumped in the assembly.
Fix: use zero instead of a symbol subtraction for Compile Unit 0.

llvm-svn: 174479
2013-02-06 00:59:41 +00:00
Eli Bendersky 59a6fb0381 Test for r174446
llvm-svn: 174464
2013-02-05 23:31:48 +00:00
Manman Ren 4e042a6be6 Dwarf: support for LTO where a single object file can have multiple line tables
We generate one line table for each compilation unit in the object file.
Reviewed by Eric and Kevin.

rdar://problem/13067005

llvm-svn: 174445
2013-02-05 21:52:47 +00:00
Akira Hatanaka dec25266d7 [mips] Do not use function CC_MipsN_VarArg unless the function being analyzed
is a vararg function.

The original code was examining flag OutputArg::IsFixed to determine whether
CC_MipsN_VarArg or CC_MipsN should be called. This is not correct, since this
flag is often set to false when the function being analyzed is a non-variadic
function.

llvm-svn: 174442
2013-02-05 21:18:11 +00:00
Benjamin Kramer 944e0abf04 InstCombine: Fix and simplify the inttoptr side too.
llvm-svn: 174438
2013-02-05 20:22:40 +00:00
Michael Gottesman a750006ad6 Added missing newline to end of test case.
llvm-svn: 174433
2013-02-05 19:39:44 +00:00
Owen Anderson de89ecf1fc Reapply r174343, with a fix for a scary DAG combine bug where it failed to differentiate between the alignment of the
base point of a load, and the overall alignment of the load.  This caused infinite loops in DAG combine with the
original application of this patch.

ORIGINAL COMMIT LOG:
When the target-independent DAGCombiner inferred a higher alignment for a load,
it would replace the load with one with the higher alignment.  However, it did
not place the new load in the worklist, which prevented later DAG combines in
the same phase (for example, target-specific combines) from ever seeing it.

This patch corrects that oversight, and updates some tests whose output changed
due to slightly different DAGCombine outputs.

llvm-svn: 174431
2013-02-05 19:24:39 +00:00
Benjamin Kramer e477875873 InstCombine: Harden code to work with vectors of pointers and simplify it a bit.
Found by running instcombine on a fabricated test case for the constant folder.

llvm-svn: 174430
2013-02-05 19:21:56 +00:00
Jyotsna Verma 6031625b03 Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns.

llvm-svn: 174429
2013-02-05 19:20:45 +00:00
Benjamin Kramer a5a9ec5755 ConstantFolding: Fix a crash when encoutering a truncating inttoptr.
This was introduced in r173293.

llvm-svn: 174424
2013-02-05 19:04:36 +00:00
Jyotsna Verma d53b25b47e Hexagon: Add testcase for post-increment store instructions.
llvm-svn: 174419
2013-02-05 18:23:51 +00:00
Chad Rosier 92a54f6d4c [SjLj Prepare] When demoting an invoke instructions to the stack, if the normal
edge is critical, then split it so we can insert the store.
rdar://13126179

llvm-svn: 174418
2013-02-05 18:23:10 +00:00
Jyotsna Verma 50ca6dd8a7 Hexagon: Use multiclass for absolute addressing mode stores.
llvm-svn: 174412
2013-02-05 18:15:34 +00:00
Jakob Stoklund Olesen eb1084ee54 Add a test case for PR14750.
This was fixed by r174402.

llvm-svn: 174405
2013-02-05 18:04:15 +00:00
Derek Schuff 90aa1d8abe [MC] Bundle alignment: Invalidate relaxed fragments
Currently, when a fragment is relaxed, its size is modified, but its
offset is not (it gets laid out as a side effect of checking whether
it needs relaxation), then all subsequent fragments are invalidated
because their offsets need to change. When bundling is enabled,
relaxed fragments need to get laid out again, because the increase in
size may push it over a bundle boundary. So instead of only
invalidating subsequent fragments, also invalidate the fragment that
gets relaxed, which causes it to get laid out again.

This patch also fixes some trailing whitespace and fixes the
bundling-related debug output of MCFragments.

llvm-svn: 174401
2013-02-05 17:55:27 +00:00
Tom Stellard 7d41161a2d R600: Add tests for instruction predicates
llvm-svn: 174393
2013-02-05 17:09:13 +00:00
Tom Stellard 2e5e7a5bef R600: Emit function name in the AsmPrinter
Emitting the function name allows us to check for it in the FileCheck
tests so we can make sure FileCheck is checking the output of the
correct function.

llvm-svn: 174392
2013-02-05 17:09:11 +00:00
Jyotsna Verma 6f635b5488 Hexagon: Add V4 compare instructions. Enable relationship mapping
for the existing instructions.

llvm-svn: 174389
2013-02-05 16:42:24 +00:00
NAKAMURA Takumi 7ec43d9b37 Formatting.
llvm-svn: 174380
2013-02-05 15:32:16 +00:00
NAKAMURA Takumi 6635fe56d3 llvm/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll: "-debug" requires +Asserts.
llvm-svn: 174379
2013-02-05 15:32:10 +00:00
Arnold Schwaighofer 22174f5d5a Loop Vectorizer: Handle pointer stores/loads in getWidestType()
In the loop vectorizer cost model, we used to ignore stores/loads of a pointer
type when computing the widest type within a loop. This meant that if we had
only stores/loads of pointers in a loop we would return a widest type of 8bits
(instead of 32 or 64 bit) and therefore a vector factor that was too big.

Now, if we see a consecutive store/load of pointers we use the size of a pointer
(from data layout).

This problem occured in SingleSource/Benchmarks/Shootout-C++/hash.cpp (reduced
test case is the first test in vector_ptr_load_store.ll).

radar://13139343

llvm-svn: 174377
2013-02-05 15:08:02 +00:00
NAKAMURA Takumi 3753b28cd2 Revert r174343, "When the target-independent DAGCombiner inferred a higher alignment for a load,"
It caused hangups in compiling clang/lib/Parse/ParseDecl.cpp and clang/lib/Driver/Tools.cpp in stage2 on some hosts.

llvm-svn: 174374
2013-02-05 14:44:16 +00:00
Logan Chien 4b724429b8 Link .ARM.exidx with corresponding text section.
The sh_link in the ELF section header of .ARM.exidx should
be filled with the section index of the corresponding text
section.

llvm-svn: 174372
2013-02-05 14:18:59 +00:00
Arnold Schwaighofer a804bbee9b ARM cost model: Cost for scalar integer casts and floating point conversions
Also adds some costs for vector integer float conversions.

llvm-svn: 174371
2013-02-05 14:05:55 +00:00
Jack Carter 428a06cc75 This patch that sets the Mips ELF header flag for
MicroMips architectures. 

Contributer: Zoran Jovanovic
 
llvm-svn: 174360
2013-02-05 09:30:03 +00:00
Jack Carter 9c1a027fe8 This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 
llvm-svn: 174358
2013-02-05 08:32:10 +00:00
Eric Christopher 6a421a944d Add support for testing the output of the abbrev table for the
skeleton CU as part of the DWARF5 split dwarf proposal.

llvm-svn: 174351
2013-02-05 07:32:00 +00:00
Eric Christopher 7a2cdf798b Add support for emitting a stub DW_AT_GNU_dwo_id as part of the
DWARF5 split dwarf proposal.

llvm-svn: 174350
2013-02-05 07:31:55 +00:00
Michael Gottesman e2376cdf71 Add code to GlobalVariable.h so that global variables marked as
externally_initialized return false for hasDefiniteInitializer and
hasUniqueInitializer.

rdar://12580965.

llvm-svn: 174345
2013-02-05 06:53:26 +00:00
Owen Anderson a47fdbb032 When the target-independent DAGCombiner inferred a higher alignment for a load,
it would replace the load with one with the higher alignment.  However, it did
not place the new load in the worklist, which prevented later DAG combines in
the same phase (for example, target-specific combines) from ever seeing it.

This patch corrects that oversight, and updates some tests whose output changed
due to slightly different DAGCombine outputs.

llvm-svn: 174343
2013-02-05 06:25:30 +00:00
Michael Gottesman 27e7ef326a Added LLVM Asm/Bitcode Reader/Writer support for new IR keyword externally_initialized.
llvm-svn: 174340
2013-02-05 05:57:38 +00:00
Manman Ren 86b1d868ba [Stack Alignment] emit warning instead of a hard error
Per discussion in rdar://13127907, we should emit a hard error only if
people write code where the requested alignment is larger than achievable
and assumes the low bits are zeros. A warning should be good enough when
we are not sure if the source code assumes the low bits are zeros.

rdar://13127907

llvm-svn: 174336
2013-02-04 23:45:08 +00:00
Jyotsna Verma 7ab68fbd1d Hexagon: Add V4 combine instructions and some more Def Pats for V2.
llvm-svn: 174331
2013-02-04 15:52:56 +00:00
Benjamin Kramer c35d526489 Disable a couple more vector splat optimizations on PPC.
I didn't see those because the test case used "not grep". FileCheck the test and
XFAIL it, preserving the old optimization, so this can be fixed eventually.

llvm-svn: 174330
2013-02-04 15:52:32 +00:00
Benjamin Kramer 2c9da989c2 X86: Open up some opportunities for constant folding by postponing shift lowering.
Fixes PR15141.

llvm-svn: 174327
2013-02-04 15:19:33 +00:00
Benjamin Kramer 548ffa274a SelectionDAG: Teach FoldConstantArithmetic how to deal with vectors.
This required disabling a PowerPC optimization that did the following:
input:
x = BUILD_VECTOR <i32 16, i32 16, i32 16, i32 16>
lowered to:
tmp = BUILD_VECTOR <i32 8, i32 8, i32 8, i32 8>
x = ADD tmp, tmp

The add now gets folded immediately and we're back at the BUILD_VECTOR we
started from. I don't see a way to fix this currently so I left it disabled
for now.

Fix some trivially foldable X86 tests too.

llvm-svn: 174325
2013-02-04 15:19:18 +00:00
Tim Northover 37b131f607 Update debugging test for change in expected metadata.
llvm-svn: 174321
2013-02-04 12:15:00 +00:00
David Blaikie 2811f8ac28 [DebugInfo] remove more node indirection (this time from the subprogram's variable lists)
llvm-svn: 174305
2013-02-04 05:56:36 +00:00
Arnold Schwaighofer 98f1012f9b ARM cost model: Penalize insertelement into D subregisters
Swift has a renaming dependency if we load into D subregisters. We don't have a
way of distinguishing between insertelement operations of values from loads and
other values. Therefore, we are pessimistic for now (The performance problem
showed up in example 14 of gcc-loops).

radar://13096933

llvm-svn: 174300
2013-02-04 02:52:05 +00:00
David Blaikie 33111dfea0 Remove the (apparently) unnecessary debug info metadata indirection.
The main lists of debug info metadata attached to the compile_unit had an extra
layer of metadata nodes they went through for no apparent reason. This patch
removes that (& still passes just as much of the GDB 7.5 test suite). If anyone
can show evidence as to why these extra metadata nodes are there I'm open to
reverting this patch & documenting why they're there.

llvm-svn: 174266
2013-02-02 05:56:24 +00:00
Reed Kotler f8933f83f0 Start static relocation implementation for mips16.
This checkin makes hello world work. 

llvm-svn: 174264
2013-02-02 04:07:35 +00:00
Manman Ren 053e4ff008 Removing ssp and uwtable from the testcase
llvm-svn: 174259
2013-02-02 01:34:38 +00:00
Shuxin Yang cadd8a068e rdar://13126763
Fix a bug in DAGCombine. The symptom is mistakenly optimizing expression
"x + x*x" into "x * 3.0".

llvm-svn: 174239
2013-02-02 00:22:03 +00:00
Manman Ren e697d3cd2e [Dwarf] avoid emitting multiple AT_const_value for static memebers.
Testing case is reduced from MultiSource/BenchMarks/Prolangs-C++/deriv1.

rdar://problem/13071590

llvm-svn: 174235
2013-02-01 23:54:37 +00:00
Bill Schmidt 52742c25ae LLVM enablement for some older PowerPC CPUs
llvm-svn: 174230
2013-02-01 22:59:51 +00:00