Commit Graph

18442 Commits

Author SHA1 Message Date
Bill Schmidt 6631e94838 Fix bug 14779 for passing anonymous aggregates [patch by Kai Nacke].
The PPC backend doesn't handle these correctly.  This patch uses logic
similar to that in the X86 and ARM backends to track these arguments
properly.

llvm-svn: 175635
2013-02-20 17:31:41 +00:00
Jyotsna Verma 7503a62bce Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.
Add HexagonMCInst class which adds various Hexagon VLIW annotations.
In addition, this class also includes some APIs related to the
constant extenders.

llvm-svn: 175634
2013-02-20 16:13:27 +00:00
Bill Schmidt 51e7951e24 Fix PR15155: lost vadd/vsplat optimization.
During lowering of a BUILD_VECTOR, we look for opportunities to use a
vector splat.  When the splatted value fits in 5 signed bits, a single
splat does the job.  When it doesn't fit in 5 bits but does fit in 6,
and is an even value, we can splat on half the value and add the result
to itself.

This last optimization hasn't been working recently because of improved
constant folding.  To circumvent this, create a pseudo VADD_SPLAT that
can be expanded during instruction selection.

llvm-svn: 175632
2013-02-20 15:50:31 +00:00
Elena Demikhovsky 0ccdd1315b I optimized the following patterns:
sext <4 x i1> to <4 x i64>
 sext <4 x i8> to <4 x i64>
 sext <4 x i16> to <4 x i64>
 
I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns:
 (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
 
 The sext_in_reg (v4i32 x) may be lowered to shl+sar operations.
 The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution.

I also added a cost of this operations to the AVX costs table.

llvm-svn: 175619
2013-02-20 12:42:54 +00:00
Kostya Serebryany 699ac28aa5 [asan] instrument invoke insns with noreturn attribute (as well as call insns)
llvm-svn: 175617
2013-02-20 12:35:15 +00:00
Logan Chien 53c18d8ac7 Fix thumbv5e frame lowering assertion failure.
It is possible that frame pointer is not found in the
callee saved info, thus FramePtrSpillFI may be incorrect
if we don't check the result of hasFP(MF).

Besides, if we enable the stack coloring algorithm, there
will be an assertion to ensure the slot is live.  But in
the test case, %var1 is not live in the prologue of the
function, and we will get the assertion failure.

Note: There is similar code in ARMFrameLowering.cpp.
llvm-svn: 175616
2013-02-20 12:21:33 +00:00
Bill Wendling 4cdb88983d Use the attribute group reference instead of the attribute directly.
llvm-svn: 175609
2013-02-20 07:48:23 +00:00
Bill Wendling 90bc19cd91 Modify the LLVM assembly output so that it uses references to represent function attributes.
This makes the LLVM assembly look better. E.g.:

     define void @foo() #0 { ret void }
     attributes #0 = { nounwind noinline ssp }

llvm-svn: 175605
2013-02-20 07:21:42 +00:00
Reed Kotler 7b503c2b03 Expand pseudos/macros:
SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16
$T8 shows up as register $24 when emitted from C++ code so we had
to change some tests that were already there for this functionality.

llvm-svn: 175593
2013-02-20 05:45:15 +00:00
Michael J. Spencer 6a8746b7e6 [llvm-readobj] Add ELF .dynamic table dumping.
llvm-svn: 175592
2013-02-20 02:37:12 +00:00
Chad Rosier 45a52fa097 [ms-inline asm] Force the use of a base pointer if the MachineFunction includes
MS-style inline assembly.

This is a follow-on to r175334.  Forcing a FP to be emitted doesn't ensure it
will be used.  Therefore, force the base pointer as well.  We now treat MS
inline assembly in the same way we treat functions with dynamic stack
realignment and VLAs.  This guarantees the BP will be used to reference 
parameters and locals.
rdar://13218191

llvm-svn: 175576
2013-02-19 23:50:45 +00:00
Jack Carter 10c97e5ca0 ELF symbol table field st_other support,
excluding visibility bits.

Mips (o32 abi) specific e_header setting.

EF_MIPS_ABI_O32 needs to be set in the 
ELF header flags for o32 abi output.

Contributer: Reed Kotler
llvm-svn: 175569
2013-02-19 22:29:00 +00:00
Jack Carter 1ba1f3cec8 ELF symbol table field st_other support,
excluding visibility bits.

Mips (Mips16) specific e_header setting.

EF_MIPS_ARCH_ASE_M16 needs to be set in the 
ELF header flags for Mips16.

Contributer: Reed Kotler
llvm-svn: 175566
2013-02-19 22:14:34 +00:00
Nadav Rotem 0186347c4c Fix a bug in mayHaveSideEffects. Functions that do not return are now considered as instructions with side effects.
rdar://13227456

llvm-svn: 175553
2013-02-19 20:02:09 +00:00
Jim Grosbach 3fa275e6f7 ARM: Allocation hints must make sure to be in the alloc order.
When creating an allocation hint for a register pair, make sure the hint
for the physical register reference is still in the allocation order.

rdar://13240556

llvm-svn: 175541
2013-02-19 18:55:36 +00:00
Eli Bendersky c66b7b2582 Fix typo
llvm-svn: 175530
2013-02-19 17:11:48 +00:00
Benjamin Kramer b3aa2b8497 Fix GCMetadaPrinter::finishAssembly not executed, patch by Yiannis Tsiouris.
Due to the execution order of doFinalization functions, the GC information were
deleted before AsmPrinter::doFinalization was executed. Thus, the
GCMetadataPrinter::finishAssembly was never called.

The patch fixes that by moving the code of the GCInfoDeleter::doFinalization to
Printer::doFinalization.

llvm-svn: 175528
2013-02-19 16:51:44 +00:00
Arnold Schwaighofer e5083442b2 ARM NEON: Merge a f32 bitcast of a v2i32 extractelt
A vectorized sitfp on doubles will get scalarized to a sequence of an
extract_element of <2 x i32>, a bitcast to f32 and a sitofp.
Due to the the extract_element, and the bitcast we will uneccessarily generate
moves between scalar and vector registers.

The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract
the element from the vector instead.

radar://13191881

llvm-svn: 175520
2013-02-19 15:27:05 +00:00
Kostya Serebryany 3ece9beaf1 [asan] instrument memory accesses with unusual sizes
This patch makes asan instrument memory accesses with unusual sizes (e.g. 5 bytes or 10 bytes), e.g. long double or
packed structures.
Instrumentation is done with two 1-byte checks
(first and last bytes) and if the error is found
__asan_report_load_n(addr, real_size) or
__asan_report_store_n(addr, real_size)
is called.

Also, call these two new functions in memset/memcpy
instrumentation.

asan-rt part will follow.

llvm-svn: 175507
2013-02-19 11:29:21 +00:00
Reed Kotler 3e457f505e Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,
BtnezT8SltiX16, BtnezT8SltiuX16 .

llvm-svn: 175486
2013-02-19 03:56:57 +00:00
Bill Wendling c98e4fef1a Temporarily revert r175470 for more review.
llvm-svn: 175476
2013-02-19 00:52:45 +00:00
Reed Kotler d82171990f Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.
llvm-svn: 175474
2013-02-19 00:20:58 +00:00
Bill Wendling 66651e4c2f Check to see if the 'no-builtin' attribute is set before simplifying a library call.
llvm-svn: 175470
2013-02-18 23:17:16 +00:00
Chad Rosier f666b761bd Comment out the rdar number.
llvm-svn: 175460
2013-02-18 21:59:15 +00:00
Chad Rosier f3f8f443e1 [fast-isel] Remove an invalid assert.
If the memcpy has an odd length with an alignment of 2, this would incorrectly
assert on the last 1 byte copy.
rdar://13202135

llvm-svn: 175459
2013-02-18 21:46:28 +00:00
Benjamin Kramer 53bc37ca2a Support for HiPE-compatible code emission, patch by Yiannis Tsiouris.
llvm-svn: 175457
2013-02-18 20:55:12 +00:00
Vincent Lejeune 1ce13f553e R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern
llvm-svn: 175446
2013-02-18 14:11:28 +00:00
Kostya Serebryany 7ca384bc1a [asan] revert r175266 as it breaks code with packed structures. supporting long double will require a more general solution
llvm-svn: 175442
2013-02-18 13:47:02 +00:00
Tim Northover 67d3c09332 AArch64: adjust tests which rely on a default JIT
Profiling tests *do* need a JIT. They'll pass if a cross-compiler targetting
AArch64 by default has been built, but fail if a native AArch64 compiler has
been build. Therefore XFAIL is inappropriate and we mark them unsupported.

ExecutionEngine tests are JIT by definition, they should also be unsupported.

Transforms/LICM only uses the interpreter to check the output is still sane
after optimisation. It can be switched to use an interpreter.

llvm-svn: 175433
2013-02-18 11:08:37 +00:00
Reed Kotler 1460738710 Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.
llvm-svn: 175420
2013-02-18 05:43:03 +00:00
Reed Kotler c40f4e5899 Expand pseudo/macro BteqzT8SltX16.
llvm-svn: 175417
2013-02-18 04:04:26 +00:00
Reed Kotler 7e4bc6067b Expand macro/pseudo BteqzT8CmpX16.
llvm-svn: 175416
2013-02-18 03:06:29 +00:00
Reed Kotler cb37409b92 Beginning of expanding all current mips16 macro/pseudo instruction sequences.
This expansion will be moved to expandISelPseudos as soon as I can figure
out how to do that. There are other instructions which use this 
ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all,
I will delete the macro asm string text so it has no way to be used
in the future.

llvm-svn: 175413
2013-02-18 00:59:04 +00:00
Richard Osborne 53fff94527 [XCore] Add missing 2r instructions.
These instructions are not targeted by the compiler but it is needed for
the MC layer.

llvm-svn: 175407
2013-02-17 22:38:05 +00:00
Richard Osborne f5a3ffcba9 [XCore] Add TSETR instruction.
This instruction is not targeted by the compiler but it is needed for the
MC layer.

llvm-svn: 175406
2013-02-17 22:32:41 +00:00
Richard Osborne 2192615d9f [XCore] Add missing u10 / lu10 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 175404
2013-02-17 20:44:48 +00:00
Richard Osborne 3814491fb1 [XCore] Add missing u6 / lu6 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 175403
2013-02-17 20:43:17 +00:00
Benjamin Kramer fb9ea4e659 Force a cpu for test. It failed on atom due to different scheduling decisions.
llvm-svn: 175401
2013-02-17 18:26:11 +00:00
Hal Finkel 76e65e4542 BBVectorize: Fix an invalid reference bug
This fixes PR15289. This bug was introduced (recently) in r175215; collecting
all std::vector references for candidate pairs to delete at once is invalid
because subsequent lookups in the owning DenseMap could invalidate the
references.

bugpoint was able to reduce a useful test case. Unfortunately, because whether
or not this asserts depends on memory layout, this test case will sometimes
appear to produce valid output. Nevertheless, running under valgrind will
reveal the error.

llvm-svn: 175397
2013-02-17 15:59:26 +00:00
Bill Wendling 23242098e7 The transform is:
(or (bool?A:B),(bool?C:D)) --> (bool?(or A,C):(or B,D))

By the time the OR is visited, both the SELECTs have been visited and not
optimized and the OR itself hasn't been transformed so we do this transform in
the hopes that the new ORs will be optimized.

The transform is explicitly disabled for vector-selects until "codegen matures
to handle them better".

Patch by Muhammad Tauqir!

llvm-svn: 175380
2013-02-16 23:41:36 +00:00
Benjamin Kramer 64bf78046e MCParser: Reject .balign with non-pow2 alignments.
GNU as rejects them and there are configure scripts in the wild that check if
the assembler rejects ".align 3" to determine whether the alignment is in bytes
or powers of two.

llvm-svn: 175360
2013-02-16 15:00:16 +00:00
Jakub Staszak 6a62c29f6b Replace "check:" wth "CHECK:".
Also fix one test by changing "vpermilps" to "vpshufd".

llvm-svn: 175357
2013-02-16 12:16:56 +00:00
Bill Wendling 61375d8953 Reinitialize the ivars in the subtarget so that they can be reset with the new features.
llvm-svn: 175336
2013-02-16 01:36:26 +00:00
Chad Rosier 925c9b499e [ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly.
If the frame pointer is omitted, and any stack changes occur in the inline
assembly, e.g.: "pusha", then any C local variable or C argument references
will be incorrect.  

I pass no judgement on anyone who would do such a thing. ;)
rdar://13218191

llvm-svn: 175334
2013-02-16 01:25:28 +00:00
Joerg Sonnenberger e2bb314a30 Derive ELF section type from the name in some cases where GNU as does
so.

llvm-svn: 175327
2013-02-16 00:32:53 +00:00
Bill Wendling e9434778f7 Temporary revert of 175320.
llvm-svn: 175322
2013-02-15 23:22:32 +00:00
Bill Wendling a060d0efd8 Reinitialize the ivars in the subtarget.
When we're recalculating the feature set of the subtarget, we need to have the
ivars in their initial state.

llvm-svn: 175320
2013-02-15 23:18:01 +00:00
Derek Schuff 8878bcc9e7 If bundle alignment is enabled, do not add data to a fragment with instructions
With bundle alignment, instructions all get their own MCFragments
(unless they are in a bundle-locked group). For instructions with
fixups, this is an MCDataFragment. Emitting actual data (e.g. for
.long) attempts to re-use MCDataFragments, which we don't want int
this case since it leads to fragments which exceed the bundle size.
So, don't reuse them in this case.
Also adds a test and fixes some formatting.

llvm-svn: 175316
2013-02-15 22:50:52 +00:00
Pekka Jaaskelainen 62848c9c24 Forgot to 'svn add' the LoopVectorizer tests for the new parallel loop metadata, sorry.
llvm-svn: 175311
2013-02-15 21:50:19 +00:00
Paul Redmond f29ddfe93f enable SDISel sincos optimization for GNU environments
- add sincos to runtime library if target triple environment is GNU
- added canCombineSinCosLibcall() which checks that sincos is in the RTL and
  if the environment is GNU then unsafe fpmath is enabled (required to
  preserve errno)
- extended sincos-opt lit test

Reviewed by: Hal Finkel

llvm-svn: 175283
2013-02-15 18:45:18 +00:00
Arnaud A. de Grandmaison 61c167c62b Teach InstCombine to work with smaller legal types in icmp (shl %v, C1), C2
It enables to work with a smaller constant, which is target friendly for those which can compare to immediates.
It also avoids inserting a shift in favor of a trunc, which can be free on some targets.

This used to work until LLVM-3.1, but regressed with the 3.2 release.

llvm-svn: 175270
2013-02-15 14:35:47 +00:00
Kostya Serebryany a968568165 [asan] support long double on 64-bit. See https://code.google.com/p/address-sanitizer/issues/detail?id=151
llvm-svn: 175266
2013-02-15 12:46:06 +00:00
Tim Northover 3533ad6bbd AArch64: remove ConstantIsland pass & put literals in separate section.
This implements the review suggestion to simplify the AArch64 backend. If we
later discover that we *really* need the extra complexity of the
ConstantIslands pass for performance reasons it can be resurrected.

llvm-svn: 175258
2013-02-15 09:33:43 +00:00
Tim Northover 5466e36fb5 AArch64: refactor frame handling to use movz/movk for overlarge offsets.
In the near future litpools will be in a different section, which means that
any access to them is at least two instructions. This makes the case for a
movz/movk pair (if total offset <= 32-bits) even more compelling.

llvm-svn: 175257
2013-02-15 09:33:26 +00:00
Bill Wendling 26b95756c1 Simplify the 'operator<' for the attribute object.
llvm-svn: 175252
2013-02-15 05:25:26 +00:00
Anna Zaks 269d1fa991 Revert "Fix testcase for attribute ordering."
This reverts commit 58f20a3cbfca7384fe5e25e095f18572736a4792.

llvm-svn: 175249
2013-02-15 04:15:53 +00:00
Anna Zaks 61040b915d Revert "Fix testcase for attribute ordering."
This reverts commit 997c6516ca161073a1d516ebca7c0ca7722f64e2.

llvm-svn: 175248
2013-02-15 04:15:50 +00:00
Bill Wendling f7d8d767fb Fix testcase for attribute ordering.
llvm-svn: 175238
2013-02-15 01:04:46 +00:00
Reed Kotler f022147790 Fix minor mips16 issues in directives for function prologue. Probably this does
not matter but makes it more gcc compatible which avoids possible subtle
problems. Also, turned back on a disabled check in helloworld.ll. 

llvm-svn: 175237
2013-02-15 01:04:38 +00:00
Bill Wendling fa1d248ccf Fix testcase for attribute ordering.
llvm-svn: 175236
2013-02-15 00:58:25 +00:00
Joel Jones 0f8617b17e The ARM NEON vector compare instructions take three arguments. However, the
assembler should also accept a two arg form, as the docuemntation specifies that
the first (destination) register is optional.

This patch uses TwoOperandAliasConstraint to add the two argument form.

It also fixes an 80-column formatting problem in:
  test/MC/ARM/neon-bitwise-encoding

<rdar://problem/12909419> Clang rejects ARM NEON assembly instructions

llvm-svn: 175221
2013-02-14 23:18:40 +00:00
Kay Tiong Khoo 7b564da474 death to extra whitespace
llvm-svn: 175200
2013-02-14 19:15:14 +00:00
Kay Tiong Khoo f809c6491d added basic support for Intel ADX instructions
-feature flag, instructions definitions, test cases

llvm-svn: 175196
2013-02-14 19:08:21 +00:00
Nadav Rotem 495b1a43c1 Dont merge consecutive loads/stores into vectors when noimplicitfloat is used.
llvm-svn: 175190
2013-02-14 18:28:52 +00:00
Weiming Zhao c598700788 Re-apply r175088 for bug fix 13622: Add paired register support for
inline asm with 64-bit data on ARM

Update test case to use -mtriple=arm-linux-gnueabi

llvm-svn: 175186
2013-02-14 18:10:21 +00:00
Vincent Lejeune f940fd05bd R600: Do not fold single instruction with more that 3 kcache read
It fixes around 100 tfb piglit tests and 16 glean tests.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175183
2013-02-14 16:57:19 +00:00
Rafael Espindola 86d5345988 Revert r15266. This fixes llvm.org/pr15266.
llvm-svn: 175173
2013-02-14 16:23:08 +00:00
Krzysztof Parzyszek f71a69d608 Add testcase for llvm-dwarfdump to test parsing of the pubnames data.
llvm-svn: 175168
2013-02-14 16:10:58 +00:00
Kristof Beyls 2efb59a719 Make ARMAsmParser accept the correct alignment specifier syntax in instructions.
The parser will now accept instructions with alignment specifiers written like
    vld1.8  {d16}, [r0:64]
, while also still accepting the incorrect syntax
    vld1.8  {d16}, [r0, :64]

llvm-svn: 175164
2013-02-14 14:46:12 +00:00
Elena Demikhovsky 5b9d426907 Moved line-info.ll to DebugInfo\X86 directory
llvm-svn: 175150
2013-02-14 09:07:34 +00:00
Elena Demikhovsky 70247a807b The test failed on Windows. I've changed the platform to run to "x86_64-apple-darwin".
llvm-svn: 175146
2013-02-14 08:23:08 +00:00
Elena Demikhovsky d0a0cc80cd Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).
Added a test.

llvm-svn: 175144
2013-02-14 08:20:26 +00:00
Michel Danzer 51d5eb2f63 R600: Add lit tests for texture sampling instruction selection.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175138
2013-02-14 07:43:51 +00:00
Andrew Trick 6871e5f4e5 Reapply "s/grep/FileCheck/ in some tests"
This reverts commit fd1335e982bbf93c5f450ed4fd29f9f787435c85.

Use a triple this time.

llvm-svn: 175134
2013-02-14 03:45:08 +00:00
Nick Lewycky 06417743cf Teach the DataLayout aware constant folder to be much more aggressive towards
'and' instructions. This is a pattern that shows up a lot in ubsan binaries.

llvm-svn: 175128
2013-02-14 03:23:37 +00:00
Andrew Trick 836bf1526b Revert "s/grep/FileCheck/ in some tests"
This reverts commit 8b75e6bc35fb3f9c1e788dbd05084c0f4a60a0f3.

The FileCheck tests are not equivalent:

test/CodeGen/X86/tailcall-structret.ll:6:10: error: expected string not found in input
; CHECK: jmp init
         ^
<stdin>:1:2: note: scanning from here
 .section __TEXT,__text,regular,pure_instructions
 ^
<stdin>:13:2: note: possible intended match here
 jmp _init ## TAILCALL
 ^

llvm-svn: 175124
2013-02-14 03:00:57 +00:00
Weiming Zhao 090edf7e67 temporarily revert the patch due to some conflicts
llvm-svn: 175107
2013-02-13 23:24:40 +00:00
Anshuman Dasgupta e96f804eba Hexagon: add support for predicate-GPR copies.
llvm-svn: 175102
2013-02-13 22:56:34 +00:00
Tom Stellard 91da4e9199 R600: Add support for 128-bit parameters
NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175096
2013-02-13 22:05:20 +00:00
Eli Bendersky 3ffeb68dd7 s/grep/FileCheck/ in some tests
llvm-svn: 175093
2013-02-13 22:00:37 +00:00
Eli Bendersky 04553985d7 s/grep/FileCheck/ in some tests
llvm-svn: 175089
2013-02-13 21:46:38 +00:00
Weiming Zhao 0632a4b002 Bug fix 13622: Add paired register support for inline asm with 64-bit data on ARM
llvm-svn: 175088
2013-02-13 21:43:02 +00:00
Chad Rosier da05cf7ba7 [ms-inline asm] Fix up test case for non-Darwin platforms.
llvm-svn: 175087
2013-02-13 21:41:58 +00:00
Jyotsna Verma d92252469e Hexagon: Use absolute addressing mode loads/stores for global+offset
instead of redefining separate instructions for them.

llvm-svn: 175086
2013-02-13 21:38:46 +00:00
Chad Rosier 282edd7caa [ms-inline-asm] Add support for memory references that have non-immediate
displacements.
rdar://12974533

llvm-svn: 175083
2013-02-13 21:33:44 +00:00
Reed Kotler f662cff689 For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.

llvm-svn: 175073
2013-02-13 20:28:27 +00:00
Manman Ren 7a4c8a783c Clean up LDV, no functionality change.
Remove dead functions: renameRegister
Move private member variables from LDV to Impl
Remove ssp/uwtable from testing case

llvm-svn: 175072
2013-02-13 20:23:48 +00:00
David Peixotto 6eecb28d3a PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA
Fixed bug in tablegen conversion when source pseudo instruction has
a different number of arguments than the destination instruction.

llvm-svn: 175066
2013-02-13 19:21:47 +00:00
Benjamin Kramer 8e2637e2b0 X86: Disable generation of rep;movsl when %esi is used as a base pointer.
This happens when there is both stack realignment and a dynamic alloca in the
function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the
base pointer and the next register spill will write into oblivion.

Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas
and freebsd a 4 byte stack alignment.

llvm-svn: 175057
2013-02-13 13:40:35 +00:00
Reed Kotler 9cb8e7b9f5 Make jumptables work for -static
llvm-svn: 175044
2013-02-13 08:32:14 +00:00
Elena Demikhovsky 9e0df7cb01 Prevent insertion of "vzeroupper" before call that preserves YMM registers, since a caller uses preserved registers across the call.
llvm-svn: 175043
2013-02-13 08:02:04 +00:00
Eric Christopher 389ee71b0a Check i1 as well as i8 variables for 8 bit registers for x86 inline
assembly.

llvm-svn: 175036
2013-02-13 06:01:05 +00:00
Eric Christopher 2398a9a175 Finish obviously broken thought.
llvm-svn: 175035
2013-02-13 06:01:00 +00:00
Kostya Serebryany 3838f27905 [tsan] disable load widening in ThreadSanitizer mode
llvm-svn: 175034
2013-02-13 05:59:45 +00:00
Manman Ren f019cd62da Debug Info: LiveDebugVarible can remove DBG_VALUEs, make sure we emit them back.
RegisterCoalescer used to depend on LiveDebugVariable. LDV removes DBG_VALUEs
without emitting them at the end.

We fix this by removing LDV from RegisterCoalescer. Also add an assertion to
make sure we call emitDebugValues if DBG_VALUEs are removed at
runOnMachineFunction.

rdar://problem/13183203
Reviewed by Andy & Jakob

llvm-svn: 175023
2013-02-13 01:14:49 +00:00
Krzysztof Parzyszek 5974de4e7d Remove target-specific info from the testcase for DWARF/pubnames.
llvm-svn: 174992
2013-02-12 18:53:21 +00:00
Chad Rosier f72d06a919 [ms-inline asm] Add support for lexing binary integers with a [bB] suffix.
This is complicated by backward labels (e.g., 0b can be both a backward label
and a binary zero).  The current implementation assumes [0-9]b is always a
label and thus it's possible for 0b and 1b to not be interpreted correctly for
ms-style inline assembly.  However, this is relatively simple to fix in the
inline assembly (i.e., drop the [bB]).

This patch also limits backward labels to [0-9]b, so that only 0b and 1b are
ambiguous.
Part of rdar://12470373

llvm-svn: 174983
2013-02-12 18:29:02 +00:00
Krzysztof Parzyszek 228daa6986 Allow optionally generating pubnames section in DWARF info. Introduce
option "generate-dwarf-pubnames" to control it, set to "false" by default.

llvm-svn: 174981
2013-02-12 18:00:14 +00:00
Kay Tiong Khoo c5c9713fcf added test cases for r174920 (prefetch disassembly)
llvm-svn: 174979
2013-02-12 17:07:44 +00:00
Paul Redmond 7e7e3de43d Fix the lit test added in r174972
Patch by: Kevin Schoedel

llvm-svn: 174974
2013-02-12 16:07:27 +00:00