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238 Commits

Author SHA1 Message Date
Sandeep Patel 7460e0822f Fix method name in comment, per Bob Wilson. 
llvm-svn: 84017
 2009-10-13 20:25:58 +00:00
Sandeep Patel 423e42b371 Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
llvm-svn: 84009
 2009-10-13 18:59:48 +00:00
Bob Wilson 84e7967fae Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. 
llvm-svn: 83600
 2009-10-09 00:01:36 +00:00
Bob Wilson c409030838 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. 
llvm-svn: 83598
 2009-10-08 23:51:31 +00:00
Bob Wilson b851eb356a Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
llvm-svn: 83596
 2009-10-08 23:38:24 +00:00
Bob Wilson 38ba47225a Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
 2009-10-08 22:53:57 +00:00
Bob Wilson cf54e934f8 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
llvm-svn: 83585
 2009-10-08 22:27:33 +00:00
Bob Wilson c2728f44a9 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
llvm-svn: 83568
 2009-10-08 18:56:10 +00:00
Bob Wilson fac9476589 Clean up some unnecessary initializations. 
llvm-svn: 83566
 2009-10-08 18:52:56 +00:00
Bob Wilson 4facd965bd Clean up a comment (indentation was wrong). 
llvm-svn: 83565
 2009-10-08 18:51:31 +00:00
Bob Wilson b6b0ab6117 Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83526
 2009-10-08 05:18:18 +00:00
Bob Wilson 71387b4b2f Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83518
 2009-10-08 00:28:28 +00:00
Bob Wilson d4f5670096 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83513
 2009-10-08 00:21:01 +00:00
Bob Wilson 32cc4ec304 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83508
 2009-10-07 23:54:04 +00:00
Bob Wilson 5ef3c6d9f4 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83506
 2009-10-07 23:39:57 +00:00
Bob Wilson 763be1a248 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83502
 2009-10-07 22:57:01 +00:00
Bob Wilson e7ef4a9a6b Add codegen support for NEON vst4 intrinsics with 128-bit vectors. 
llvm-svn: 83486
 2009-10-07 20:49:18 +00:00
Bob Wilson 23464866ad Add codegen support for NEON vst3 intrinsics with 128-bit vectors. 
llvm-svn: 83484
 2009-10-07 20:30:08 +00:00
Bob Wilson 3dcb5377ef Add codegen support for NEON vst2 intrinsics with 128-bit vectors. 
llvm-svn: 83482
 2009-10-07 18:47:39 +00:00
Bob Wilson ab3a9474d6 Add codegen support for NEON vld4 intrinsics with 128-bit vectors. 
llvm-svn: 83479
 2009-10-07 18:09:32 +00:00
Bob Wilson 6bbefc2f67 Add codegen support for NEON vld3 intrinsics with 128-bit vectors. 
llvm-svn: 83471
 2009-10-07 17:24:55 +00:00
Bob Wilson 99e80228a9 Rearrange code for selecting vld2 intrinsics. No functionality change. 
This is just to be more consistent with the forthcoming code for vld3/4.

llvm-svn: 83470
 2009-10-07 17:23:09 +00:00
Bob Wilson e6b778d5ff Add codegen support for NEON vld2 operations on quad registers. 
llvm-svn: 83422
 2009-10-06 22:01:59 +00:00
Bob Wilson 2dd957fff6 Pass the optimization level when constructing the ARM instruction selector. 
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel.  Radar 7250345.

llvm-svn: 82988
 2009-09-28 14:30:20 +00:00
Anton Korobeynikov 7c2b1e71c1 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. 
This should be better than single load from constpool.

llvm-svn: 82948
 2009-09-27 23:52:58 +00:00
Dan Gohman 32f71d714b Rename getTargetNode to getMachineNode, for consistency with the 
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.

llvm-svn: 82790
 2009-09-25 18:54:59 +00:00
Bob Wilson d7797754d4 Add support for generating code for vst{234}lane intrinsics. 
llvm-svn: 80707
 2009-09-01 18:51:56 +00:00
Bob Wilson da9817cddd Generate code for vld{234}_lane intrinsics. 
llvm-svn: 80656
 2009-09-01 04:26:28 +00:00
Bob Wilson e0636a7aed Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations. 
The instructions can be selected directly from the intrinsics.  We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.

llvm-svn: 80117
 2009-08-26 17:39:53 +00:00
Devang Patel 0939595711 Record variable debug info at ISel time directly. 
llvm-svn: 79742
 2009-08-22 17:12:53 +00:00
Anton Korobeynikov 232b19c3d5 Fix some typos and use type-based isel for VZIP/VUZP/VTRN 
llvm-svn: 79625
 2009-08-21 12:41:42 +00:00
Anton Korobeynikov ce3ff1be8a Add nodes & dummy matchers for some v{zip,uzp,trn} instructions 
llvm-svn: 79622
 2009-08-21 12:40:50 +00:00
Bob Wilson 51c7aa04ec Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as 
vector shuffles.  Temporarily remove the tests for these operations until the
new implementation is working.

llvm-svn: 79579
 2009-08-21 00:01:42 +00:00
Evan Cheng 9a58aff837 Indentation. 
llvm-svn: 79022
 2009-08-14 19:01:37 +00:00
Bob Wilson cce31f6831 During legalization, change Neon vdup_lane operations from shuffles to 
target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.

llvm-svn: 78993
 2009-08-14 05:08:32 +00:00
Owen Anderson 55f1c09e31 Push LLVMContexts through the IntegerType APIs. 
llvm-svn: 78948
 2009-08-13 21:58:54 +00:00
Evan Cheng bb2af3555c Shrink Thumb2 movcc instructions. 
llvm-svn: 78790
 2009-08-12 05:17:19 +00:00
Bob Wilson f042eadd1e Add missing chain operands for VLD* and VST* instructions. 
Set "mayLoad" and "mayStore" on the load/store instructions.

llvm-svn: 78761
 2009-08-12 00:49:01 +00:00
Evan Cheng f6a9d06241 Shrinkify Thumb2 r = add sp, imm. 
llvm-svn: 78745
 2009-08-11 23:00:31 +00:00
Owen Anderson 9f94459d24 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
 2009-08-11 20:47:22 +00:00
Jim Grosbach f24f9d9cb6 Whitespace cleanup. Remove trailing whitespace. 
llvm-svn: 78666
 2009-08-11 15:33:49 +00:00
Evan Cheng 3606467709 Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to 
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.

llvm-svn: 78658
 2009-08-11 08:52:18 +00:00
Bob Wilson 12842f9865 Use vAny type to get rid of Neon intrinsics that differed only in whether 
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.

llvm-svn: 78646
 2009-08-11 05:39:44 +00:00
Dan Gohman 733a64db57 Fix a bug where DAGCombine was producing an illegal ConstantFP 
node after legalize, and remove the workaround code from the
ARM backend.

llvm-svn: 78615
 2009-08-10 23:15:10 +00:00
Owen Anderson 53aa7a960c Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
llvm-svn: 78610
 2009-08-10 22:56:29 +00:00
Evan Cheng f72c13bdf5 Handle the constantfp created during post-legalization dag combiner phase. 
llvm-svn: 78594
 2009-08-10 20:25:59 +00:00
Anton Korobeynikov 887d05ce9b Use VLDM / VSTM to spill/reload 128-bit Neon registers 
llvm-svn: 78468
 2009-08-08 13:35:48 +00:00
Bob Wilson e2231070ff Implement Neon VZIP and VUZP instructions. These are very similar to VTRN, 
so I generalized the class for VTRN in the .td file to handle all 3 of them.

llvm-svn: 78460
 2009-08-08 06:13:25 +00:00
Bob Wilson db46af0461 Implement Neon VTRN instructions. For now, anyway, these are selected 
directly from the intrinsics produced by the frontend.  If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.

llvm-svn: 78459
 2009-08-08 05:53:00 +00:00
Evan Cheng b972e5633f It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
 2009-08-07 00:34:42 +00:00