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Author SHA1 Message Date
Renato Golin 6088504499 Adding support to LLVM for targeting Cortex-A72 
Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp
load balancing pass isn't enabled for Cortex-A72 as it's not
profitable to have it enabled for this core.

Patch by Ranjeet Singh.

llvm-svn: 228140
 2015-02-04 13:31:29 +00:00
Jiangning Liu cd296378a7 Implement AArch64 TTI interface isAsCheapAsAMove. 
llvm-svn: 214159
 2014-07-29 02:09:26 +00:00